Horizontal and Vertical Flow Integration for Design and Verification System design and verification are a critical component for making products successful in an always-on and always-connected world.

Design and Verification Need a Closer Relationship Concurrent development and verification of designs is more efficient and increases corporate organizational strength.

System Design Enablement – Looking Beyond the Chip System Design Enablement (SDE) will provide tools, design content, and services for the development of whole systems or end products. ...

Structural Component Defects Screened Out By Acoustic Micro Imaging New AMI developments have made component screening more informative and more effective, a boon to the task of scrutinizing avionic...


Try IP before you buy: Real-time PPA analysis from eSilicon Get immediate answers to your power, performance or area (PPA) questions on eSilicon® memory compilers and I/Os using the IP MarketPlace™ environment (no cost or obligation). Demo video is now available. Recorded January 21, 2015.

Sponsored By:


Gabe's EDA

Cadence Introduced Tensilica Vision P5 DSP

Gabe Moretti, Senior Editor DSP devices are indispensable in electronic products that deal with the outside...

The Internet of Things

Making the 8051 Secure from Hacking in the Smart Home Internet of Things

By Jonah McLeod, Silicon Valley Blogger Jauher Zaidi, Chairman and Chief Innovation Officer of Palmchip Corp. based in...

The Canonical Hamiltonian

Part II: The Ecstasy and the Agony of UVM Abstraction and Encapsulation Featuring the AMIQ APB VIP

Part II of our tour through UVM reusability through TLM ports and the factory in the AMIQ APB VIP. by Hamilton Carter...

JB's Circuit

Is Hardware Really That Much Different From Software

When can hardware be considered as software? Are software flows less complex? Why are hardware tools less up-to-date? Experts...


Featured Solutions

PLL and DLL Hard Macros

April 9, San Jose, CA
... more

Chip Design on Facebook

Chip Design on Twitter

Datasheet Directory

    EDA Tools

    Verification Functional

  • by AMIQ EDA

    Design and Verification Tools (DVT) is an integrated development environment (IDE) for the e language, SystemVerilog, Verilog, and VHDL. It helps design and verification engineers...

  • by AMIQ EDA

    Thorough audit of your test benches Verissimo SystemVerilog Testbench Linter is a static code analysis tool that allows engineers to perform a thorough audit of their testbenches....

  • Methods / EDA Tools

  • by ClioSoft Inc.

    ClioSoft ClioSoft’s SOS Design Collaboration Platform is built to handle the complex requirements of system-on-chip design flows. The SOS platform provides a sophisticated multi-site...

  • Design-for-Test (DFT)

  • by Source III, Inc.

    Source III provides the industry’s most comprehensive and cost-effective vector translation product (VTRAN®) which links simulation/ATPG vector data to ATE, a powerful vector...

  • by Source III, Inc.

    With nearly 25 years of field-proven success, VTRAN™ offers the most cost-effective, full-feature solution to creating EDA and ATE test programs from simulation and ATPG vectors....

  • Verification

  • by Agnisys

    IDesignSpec™is an award winning Electronic Design Automation tool that allows an IP, SoC, or System Designer to create the register map specification once and automatically...

  • by Agnisys

    IDesignSpec™ is an award winning Electronic Design Automation tool that allows an IP, SoC, or System Designer to create the register map specification once and automatically...

  • by Real Intent

    Meridian CDC is the fastest, highest capacity and most precise clock domain crossing (CDC) solution in the market. It performs comprehensive structural and functional analysis...

  • by Sutherland HDL, Inc

    Founded in 1992, Sutherland HDL has trained thousands of engineers throughout the world on Verilog, SystemVerilog, SVA and UVM. WORKSHOP HIGHLIGHTS Verilog and SystemVerilog...

  • Semiconductor Technologies

    IP - Core

  • by Calypto Design Systems

    Accelerate Time to Rtl, Reduce Verification Effort
    The Catapult® high-level synthesis tool empowers designers to use industry standard ANSI C++ and SystemC to describe functional intent, and move up to a more productive abstraction level.

  • by Calypto Design Systems

    With the explosion of consumer electronics, designing for low-power has become an important design constraint and a key differentiating factor. The RTL design phase provides the ideal opportunity to dramatically reduce power, since several micro-architectural transformations can be done at this stage, both via automated tools as well as manually by the RTL designers.

  • by Calypto Design Systems

    The emergence of consumer electronics is causing a fundamental shift in Register Transfer Level (RTL) design methodologies. The race for time to market has resulted in the adoption and growth of higher level design creation methodologies. In particular, High Level Synthesis (HLS) directly from software models to hardware has become very popular.

  • by Mixel, Inc.

    Organizations: GSA, MIPI Alliance The MXL-M-PHY-MIPI is a high-frequency low-power, low-cost, Physical Layer IP compliant with the MIPI® Alliance Specification for M-PHY®....

  • by SmartDV Technologies India Private Limited

    Organizations: EDAC, GSA, EIC, OCP-IP, Si2, SPIRIT SmartDV offers wide range of Verification IP’s, Memory models and Design IP’s. Verification models include complete...

  • by True Circuits Inc.

    Organizations: GSA The TCI DDR 4/3 PHY is a high-performance, scalable system using a radically new architecture that continuously and automatically adjusts each pin individually,...

  • by True Circuits Inc.

    Organizations: GSA True Circuits’ complete family of standardized, silicon-proven, low-jitter PLL and DLL hard macros spans nearly all performance points and features typically...

IP Search

Find detailed information about thousands of commercially available IP blocks from more than 230 suppliers
Advanced Search

Affiliate Sponsors

Tech Videos


  • Download the latest issue of the Chip Design Magazine
    and subscribe to receive future issues and the email newsletter.

Chip Design Research

Are you up-to-date on important SoC and IP design trends, analysis and market forecasts?

Chip Design now offers customized market research services.

For more information contact Jenna Johnson at 612.598.3446

Calendar Of Events

  • ARM TechCon 2015

    Santa Clara Convention Center, Santa Clara, CA November 10-12, 2015

  • DesignCon

    Santa Clara Convention Center, Santa Clara, CA Jan 19-21, 2016

  • 2016 DVCon

    DoubleTree, San Jose Feb 29-Mar 3, 2016

  • IMS 2016

    San Francisco, CA May 22-27, 2016

  • DAC 2016

    Austin, TX June 5-9, 2016

©2015 Extension Media. All Rights Reserved. PRIVACY POLICY | TERMS AND CONDITIONS