TOP STORIES

REUSE 2017 Tackles Semi IP Theft and Open Hardware Keynote will highlight IP theft and prevention while afternoon panel wrestles with semi open source hardware reuse and IP. read more

60GHz technology opens door to WiGig® and 5G applications Imec’s prototype small, low power 60GHz transceiver with beamforming offered to growing communication markets. read more

Developing the Portable Stimulus Standard I took the opportunity to interview the leaders of the Accellera Working Group (WG) that is developing the new Portable Test & Stimulus Standard:  Faris Khundakjie,... read more

Embedded FPGAs Offer SoC Flexibility' By Dave Lammers, Contributing EditorIt was back in 1985 that Ross Freeman invented the FPGA, gaining a fundamental patent (#4,870,302) that promised engineers the ability to ... read more


Blogs

Pete's Posts

The ConFab 2018 Update
A new wave of growth is sweeping through the semiconductor industry, propelled by a vast array of new applications, incl...

Ed's Threads

Mott Memristor Chaos could make Efficient AI
Congratulations to Suhas Kumar, John Paul Strachan, and R. Stanley Williams of Hewlett Packard Labs in Palo Alto for sho...

IC Design

How to Build CMP Models for Hotspot Detection
blogger

By Ruben Ghulghazaryan, Jeff Wilson Mentor, a Siemens Business Over the last two decades, chemical mechanical polishing...

MEMS Industry Group

MEMS & Sensors Technical Congress 2017: Knowing Your Unknowns
By Karen Lightman, MEMS & Sensors Industry Group | SEMI As in life, knowing everything in MEMS and sensors is imp...

JB's Circuit

SEMI Pacific NW Breakfast Forum: The Future of Communication
blogger

Attention - Semiconductor professionals in the Pacific Northwest! SEMI 2017 is having another half-day breakfast...

Chipworks

Intel Unveils More 10nm Details
By Dick James On March 28, Intel held a Technology and Manufacturing Day in San Francisco, not surprisingly focusing ...





NEWS, ANALYSIS & FEATURES

Featured Solutions

Calypto SLEC Product Family

The emergence of consumer electronics is causing a fundamental shift in Register Transfer Level (RTL) design methodologies. The race for time to market has resulted in the ... more

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Datasheet Directory

    EDA Tools

    Verification Functional

  • by AMIQ EDA

    Design and Verification Tools (DVT) is an integrated development environment (IDE) for the e language, SystemVerilog, Verilog, and VHDL. It helps design and verification engineers...

  • by AMIQ EDA

    Thorough audit of your test benches Verissimo SystemVerilog Testbench Linter is a static code analysis tool that allows engineers to perform a thorough audit of their testbenches....

  • Methods / EDA Tools

  • by ClioSoft Inc.

    ClioSoft ClioSoft’s SOS Design Collaboration Platform is built to handle the complex requirements of system-on-chip design flows. The SOS platform provides a sophisticated multi-site...

  • Design-for-Test (DFT)

  • by Source III, Inc.

    Source III provides the industry’s most comprehensive and cost-effective vector translation product (VTRAN®) which links simulation/ATPG vector data to ATE, a powerful vector...

  • by Source III, Inc.

    With nearly 25 years of field-proven success, VTRAN™ offers the most cost-effective, full-feature solution to creating EDA and ATE test programs from simulation and ATPG vectors....

  • Verification

  • by Agnisys

    IDesignSpec™is an award winning Electronic Design Automation tool that allows an IP, SoC, or System Designer to create the register map specification once and automatically...

  • by Agnisys

    IDesignSpec™ is an award winning Electronic Design Automation tool that allows an IP, SoC, or System Designer to create the register map specification once and automatically...

  • by Excellicon

    Organizations: EDAC, GSA, Si2 Constraints-Manager (ConMan), Constraints-Certifier (ConCert), Exceptions Toolbox and Clock Domain Crossing Review (ConDor) End to End timing...

  • by Real Intent

    Meridian CDC is the fastest, highest capacity and most precise clock domain crossing (CDC) solution in the market. It performs comprehensive structural and functional analysis...

  • by Sutherland HDL, Inc

    Founded in 1992, Sutherland HDL has trained thousands of engineers throughout the world on Verilog, SystemVerilog, SVA and UVM. WORKSHOP HIGHLIGHTS Verilog and SystemVerilog...

  • Semiconductor Technologies

    IP - Core

  • by Calypto Design Systems

    Accelerate Time to Rtl, Reduce Verification Effort
    The Catapult® high-level synthesis tool empowers designers to use industry standard ANSI C++ and SystemC to describe functional intent, and move up to a more productive abstraction level.

  • by Calypto Design Systems

    With the explosion of consumer electronics, designing for low-power has become an important design constraint and a key differentiating factor. The RTL design phase provides the ideal opportunity to dramatically reduce power, since several micro-architectural transformations can be done at this stage, both via automated tools as well as manually by the RTL designers.

  • by Calypto Design Systems

    The emergence of consumer electronics is causing a fundamental shift in Register Transfer Level (RTL) design methodologies. The race for time to market has resulted in the adoption and growth of higher level design creation methodologies. In particular, High Level Synthesis (HLS) directly from software models to hardware has become very popular.

  • by Mixel, Inc.

    Organizations: GSA, MIPI Alliance Mixel’s MIPI C-PHY/D-PHY Combo is a high-frequency low-power, low-cost, source-synchronous, physical layer. The PHY can be configured as...

  • by Mixel, Inc.

    Organizations: GSA, MIPI Alliance D-PHY RX+ is a CSI and DSI D-PHY Receiver optimized for small area and low power, while achieving full-speed production testing, in-system...

  • by Mixel, Inc.

    Organizations: GSA, MIPI Alliance The MXL-M-PHY-MIPI is a high-frequency low-power, low-cost, Physical Layer IP compliant with the MIPI® Alliance Specification for M-PHY®....

  • by SmartDV Technologies India Private Limited

    Organizations: EDAC, GSA, EIC, OCP-IP, Si2, SPIRIT SmartDV offers wide range of Verification IP’s, Memory models and Design IP’s. Verification models include complete...

  • by True Circuits Inc.

    Organizations: GSA The TCI DDR 4/3 PHY is a high-performance, scalable system using a radically new architecture that continuously and automatically adjusts each pin individually,...

  • by True Circuits Inc.

    Organizations: GSA True Circuits’ complete family of standardized, silicon-proven, low-jitter PLL and DLL hard macros spans nearly all performance points and features typically...




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