Solid State Watch: January 23-29, 2015 Solid growth in automotive semiconductor market; $4M grant to UMass Lowell for printed and flexible electronics development; Book-to-bill ratio belo...

Changes and Challenges Abound in Multi-patterning Lithography Multi-patterning lithography is a fact of life for many chipmakers. Experts in the fields of electronic design automation and lithograph...

The Various Faces of IP Modeling Providing all the needed types of models to successfully integrate an IP component into an advanced SoC is more comple...

Solid State Watch: January 16-22, 2015 SUNY Poly announces founding president; Solving an organic semiconductor mystery; UC Berkeley Extension announces new semiconductor IC program; 2015 tec...

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Blogs

Gabe's EDA

You Ought To See This Webinar
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Gabe Moretti, Senior Editor A little over a month ago I wrote a blog about eSilicon's IP MarketPlace. On Wednesday...

The Internet of Things

Smart Fabric, Not Wrist Bling, To Lead Wearable Market Growth?
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By: Jonah McLeod, Silicon Valley Blogger There's incredible hype surrounding the wearable market and most of it is aimed...

JB's Circuit

Is Hardware Really That Much Different From Software
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When can hardware be considered as software? Are software flows less complex? Why are hardware tools less up-to-date? Experts...

The Canonical Hamiltonian

Citizen Science and The Search for Sputnik IV: Part 1
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The holiday season is once again upon us, and, as usual this time of year, my thoughts are running to stories of science...

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Featured Solutions

IDesignSpec™

IDesignSpec™ is an award winning Electronic Design Automation tool that allows an IP, SoC, or System Designer to create the register map specification once and automatically ... more

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Datasheet Directory

    EDA Tools

    Verification Functional

  • by AMIQ EDA

    Design and Verification Tools (DVT) is an integrated development environment (IDE) for the e language, SystemVerilog, Verilog, and VHDL. It helps design and verification eng

  • by AMIQ EDA

    Thorough audit of your test benches Verissimo SystemVerilog Testbench Linter is a static code analysis tool that allows engineers to perform a thorough audit of their test

  • Methods / EDA Tools

    Design-for-Test (DFT)

  • by Source III, Inc.

    With nearly 25 years of field-proven success, VTRAN™ offers the most cost-effective, full-feature solution to creating EDA and ATE test programs from simulation and ATPG ve

  • Verification

  • by Agnisys

    IDesignSpec™is an award winning Electronic Design Automation tool that allows an IP, SoC, or System Designer to create the register map specification once and automatically

  • by Agnisys

    IDesignSpec™ is an award winning Electronic Design Automation tool that allows an IP, SoC, or System Designer to create the register map specification once and automaticall

  • by Real Intent

    Meridian CDC is the fastest, highest capacity and most precise clock domain crossing (CDC) solution in the market. It performs comprehensive structural and functional analysi

  • by Sutherland HDL, Inc

    Founded in 1992, Sutherland HDL has trained thousands of engineers throughout the world on Verilog, SystemVerilog, SVA and UVM. WORKSHOP HIGHLIGHTS Verilog and System

  • Semiconductor Technologies

    IP - Core

  • by Calypto Design Systems

    Accelerate Time to Rtl, Reduce Verification Effort
    The Catapult® high-level synthesis tool empowers designers to use industry standard ANSI C++ and SystemC to describe functional intent, and move up to a more productive abstraction level.

  • by Calypto Design Systems

    With the explosion of consumer electronics, designing for low-power has become an important design constraint and a key differentiating factor. The RTL design phase provides the ideal opportunity to dramatically reduce power, since several micro-architectural transformations can be done at this stage, both via automated tools as well as manually by the RTL designers.

  • by Calypto Design Systems

    The emergence of consumer electronics is causing a fundamental shift in Register Transfer Level (RTL) design methodologies. The race for time to market has resulted in the adoption and growth of higher level design creation methodologies. In particular, High Level Synthesis (HLS) directly from software models to hardware has become very popular.

  • by Mixel, Inc.

    Organizations: GSA, MIPI Alliance The MXL-M-PHY-MIPI is a high-frequency low-power, low-cost, Physical Layer IP compliant with the MIPI® Alliance Specification for M-PHY

  • by SmartDV Technologies India Private Limited

    Organizations: EDAC, GSA, EIC, OCP-IP, Si2, SPIRIT SmartDV offers wide range of Verification IP’s, Memory models and Design IP’s. Verification models include complete

  • by True Circuits Inc.

    Organizations: GSA The TCI DDR 4/3 PHY is a high-performance, scalable system using a radically new architecture that continuously and automatically adjusts each pin indiv

  • by True Circuits Inc.

    Organizations: GSA True Circuits’ complete family of standardized, silicon-proven, low-jitter PLL and DLL hard macros spans nearly all performance points and features typi



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