TOP STORIES

Memory Class Storage for Embedded Applications Why a DRAM replacement with non-volatility bodes well for the memory roadmap’s futureIntroductionAll indications point to a dramatic shift in the availability of ... read more

A New Era for Analysis and Debug Analysis and debug have been stuck in a sequential world. Traces from a simulator or emulator define what happened while analysis and debug tools attempt to find out why they hap... read more

IoT Verification is Harder than it Looks As has been the case for at least 20 years, functional verification remains the bottleneck for semiconductor development. Many studies have shown that verification consum... read more

'Zero Touch' IoT Security Is Key to Continued Growth By now it’s clear that the IoT will miss the much-touted target of 50B connected devices by 2020. The problem? Security.IT managers are so worried about... read more


Blogs

XtremeEDA

Portable Stimulus at a Minimum
by Neil Johnson

Chief Technologist


MEMS Industry Group

When Will Self-Driving Cars Become a Reality?
By Stephen Breit, Senior Director, MEMS Business, Coventor, a Lam Research Company Self-driving cars have been all th...

Pete's Posts

AI Focus of The ConFab
Artificial Intelligence will be a focus of The ConFab 2018, to be held May 20-23 at The Cosmopolitan of Las Vegas. We’ll...

Chipworks

IEDM 2017: Intel's 10nm Platform Process
By Dick James IEDM this year was its usual mixture of academic exotica and industrial pragmatica (to use a very broad...

Ed's Threads

Mott Memristor Chaos could make Efficient AI
Congratulations to Suhas Kumar, John Paul Strachan, and R. Stanley Williams of Hewlett Packard Labs in Palo Alto for sho...

IC Design

How to Build CMP Models for Hotspot Detection
blogger

By Ruben Ghulghazaryan, Jeff Wilson Mentor, a Siemens Business Over the last two decades, chemical mechanical polishing...

JB's Circuit

SEMI Pacific NW Breakfast Forum: The Future of Communication
blogger

Attention - Semiconductor professionals in the Pacific Northwest! SEMI 2017 is having another half-day breakfast...





NEWS, ANALYSIS & FEATURES

Featured Solutions

Calypto PowerPro Product Family

With the explosion of consumer electronics, designing for low-power has become an important design constraint and a key differentiating factor. The RTL design phase provides ... more

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Datasheet Directory

    EDA Tools

    Verification Functional

  • by AMIQ EDA

    Design and Verification Tools (DVT) is an integrated development environment (IDE) for the e language, SystemVerilog, Verilog, and VHDL. It helps design and verification engineers...

  • by AMIQ EDA

    Thorough audit of your test benches Verissimo SystemVerilog Testbench Linter is a static code analysis tool that allows engineers to perform a thorough audit of their testbenches....

  • Methods / EDA Tools

  • by ClioSoft Inc.

    ClioSoft ClioSoft’s SOS Design Collaboration Platform is built to handle the complex requirements of system-on-chip design flows. The SOS platform provides a sophisticated multi-site...

  • Design-for-Test (DFT)

  • by Source III, Inc.

    Source III provides the industry’s most comprehensive and cost-effective vector translation product (VTRAN®) which links simulation/ATPG vector data to ATE, a powerful vector...

  • by Source III, Inc.

    With nearly 25 years of field-proven success, VTRAN™ offers the most cost-effective, full-feature solution to creating EDA and ATE test programs from simulation and ATPG vectors....

  • Verification

  • by Agnisys

    IDesignSpec™is an award winning Electronic Design Automation tool that allows an IP, SoC, or System Designer to create the register map specification once and automatically...

  • by Agnisys

    IDesignSpec™ is an award winning Electronic Design Automation tool that allows an IP, SoC, or System Designer to create the register map specification once and automatically...

  • by Excellicon

    Organizations: EDAC, GSA, Si2 Constraints-Manager (ConMan), Constraints-Certifier (ConCert), Exceptions Toolbox and Clock Domain Crossing Review (ConDor) End to End timing...

  • by Real Intent

    Meridian CDC is the fastest, highest capacity and most precise clock domain crossing (CDC) solution in the market. It performs comprehensive structural and functional analysis...

  • by Sutherland HDL, Inc

    Founded in 1992, Sutherland HDL has trained thousands of engineers throughout the world on Verilog, SystemVerilog, SVA and UVM. WORKSHOP HIGHLIGHTS Verilog and SystemVerilog...

  • Semiconductor Technologies

    IP - Core

  • by Calypto Design Systems

    Accelerate Time to Rtl, Reduce Verification Effort
    The Catapult® high-level synthesis tool empowers designers to use industry standard ANSI C++ and SystemC to describe functional intent, and move up to a more productive abstraction level.

  • by Calypto Design Systems

    With the explosion of consumer electronics, designing for low-power has become an important design constraint and a key differentiating factor. The RTL design phase provides the ideal opportunity to dramatically reduce power, since several micro-architectural transformations can be done at this stage, both via automated tools as well as manually by the RTL designers.

  • by Calypto Design Systems

    The emergence of consumer electronics is causing a fundamental shift in Register Transfer Level (RTL) design methodologies. The race for time to market has resulted in the adoption and growth of higher level design creation methodologies. In particular, High Level Synthesis (HLS) directly from software models to hardware has become very popular.

  • by Mixel, Inc.

    Organizations: GSA, MIPI Alliance Mixel’s MIPI C-PHY/D-PHY Combo is a high-frequency low-power, low-cost, source-synchronous, physical layer. The PHY can be configured as...

  • by Mixel, Inc.

    Organizations: GSA, MIPI Alliance D-PHY RX+ is a CSI and DSI D-PHY Receiver optimized for small area and low power, while achieving full-speed production testing, in-system...

  • by Mixel, Inc.

    Organizations: GSA, MIPI Alliance The MXL-M-PHY-MIPI is a high-frequency low-power, low-cost, Physical Layer IP compliant with the MIPI® Alliance Specification for M-PHY®....

  • by SmartDV Technologies India Private Limited

    Organizations: EDAC, GSA, EIC, OCP-IP, Si2, SPIRIT SmartDV offers wide range of Verification IP’s, Memory models and Design IP’s. Verification models include complete...

  • by True Circuits Inc.

    Organizations: GSA The TCI DDR 4/3 PHY is a high-performance, scalable system using a radically new architecture that continuously and automatically adjusts each pin individually,...

  • by True Circuits Inc.

    Organizations: GSA True Circuits’ complete family of standardized, silicon-proven, low-jitter PLL and DLL hard macros spans nearly all performance points and features typically...




Tech Videos

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