• Gabe on EDA: Real Intent Helps Designers Verify Intent
• EDACafe: A Page is Turned
• Press Release: Graham Bell Joins Real Intent to Promote Early Functional Verification & Advanced Sign-Off Circuit Design Software
• Press Release: Real Intent Demos EDA Solutions for Early Functional Verification & Advanced Sign-off at Synopsys Users Group (SNUG)
• Article: Blindsided by a glitch

• Firms Ready Chips for New Mobile Storage Standard
• DDM and PLM Tools Challenge Semiconductor IP Reuse
• Obama Visits CNSE, Calls for Tax Changes
• RF Front-End Integration Driven By Low Power
• Low-Power Undercurrents at GlobalPress 2012

iDesign - Providing the advanced IC Design market access to high-value information and essential tools.

How to Pick the Best Verification IP for Your... by Tom Hackett Sr. Product Marketing Manager, Cadence
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Fast and New Method for Cycle Slip Analysis in... by Akmarul Ariffin Salleh, Agilent Technologies
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The Next Big Challenge by By Ed Sperling, Contributing Editor
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The path forward may be more focused on matching goals at the architectural stage, and then being able to swap information as...

Embedded software test tools are a growing market by Lou Covey, editorial director
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The explosive growth of portable and wireless technology is a driver for similar growth in embedded software development...

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• Parasoft approaches comprehensive testing for embedded software

  The explosive growth of portable and wireless technology is a driver for similar growth in embedded software development....

• Automating embedded software testing with Electric Cloud

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• Strategy And Technology: One On One With Wally Rhines

  Mentor's Chairman and CEO sounds off about where the IC design challenges are, what needs to be done to fix them, and what new opportunities will unfold.

• One-On-One: Jack Harding

  eSilicon's CEO talks with System-Level Design about changes in design at advanced nodes, the power of 2.5D and 3D stacking, and how the semiconductor supply chain is changing.

• One-On-One: Naveed Sherwani

  Open-Silicon's CEO talks with System-Level Design about getting the business priorities of designing a complex SoC in line with the technology; why getting chips out the door on time is critical and why it's not happening.

• Walter Ng, GLOBALFOUNDRIES at DAC 2011 - IP Talks presenter

  Interview with Walter Ng, Vice President, IP Ecosystem, GLOBALFOUNDRIES. DAC 2011. Demonstrating 32/28nm design, 20nm technology. Design Enablement, ChipEstimate.com IP Talks 2011

• Verification: What's in Your Wallet?

  This DAC Pavilion Panel explores technical and business issues related to SoC verification by panelists from ARM, AMD and Qualcomm.

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• GlobalFoundries, Mentor Team Up on Yield Front
  Mentor Graphics announced new capabilities in its design to silicon solutions that support GLOBALFOUNDRIES’ third generation of signoff-ready design enablement for leading edge IC manufacturing. (Aug. 26, 2011)
• Cutting Out The Fat In Designs
  LTE moves by Tensilica, CEVA, focus on better efficiency and performance through deeper understanding of how a device works.
• Experts At The Table: Rapid Prototyping
  Measuring the impact of power and software on a design remain a big challenge, as does the trade-offs between commercial verses homegrown prototyping systems.
• The IEDM Logic Debate
  The just-concluded 2011 IEDM in Washington, D.C. had three tracks, to my mind, and trying to make sense of it all is a long process.

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• EdXact: Bringing Innovation Into The Verification Flow

• InCyte

• Semiconductor Technologies > IP--Core - PLL and DLL Hard Macros

• Platform Express

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• Microwave Simulation’s Widening Reach
• On-Chip Hardware-Monitoring Network Evaluates NoC Performance
• Poor Semiconductor IPOs Point to Changing Future
• IP Developers Will Play Games

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• LTE-Advanced Signal Generation and Measurement Using SystemVue

• Linking Early Mechatronic System Analysis to Physical Testing

• Best Practice Development Processes for Medical Device FPGAs

• Direct Power MOSFET Capacitance Measurement at 3000 V

• Common Pitfalls in PCI Express Design

• Increasing Revenue Through Continuously Optimized Data Center Management

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• Applied Tips Restructuring Plan in Solar and LED Units
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• Microsoft to Join 3D TSV DRAM Consortium
• Editor's View: Training Technicians, Hudson Valley Style
• Semico Spin: Forecasting Wafer Demand: Technology Migration, Bottlenecks and Confetti

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• Derivative Designs Demand Discipline
• Software Takes Control
• Editor's Note: Which Comes First?
• ESL Edge: Smarter Design Strategies

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• Power Model Complexity Grows
• Material Effects: Trading Performance For Power
• Low Power Dominates CES
• Editor's Note: Little Shifts, Big Changes
• Absolute Power: 4G LTE vs. 3G

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