• Getting Ready for DAC
• Group Forms FD-SOI Project
• Integrating sensor data acquisition in mobile apps
• Firms Lower Chip Forecasts
• Radio Gain Benefits of Ultra-Low Power and Digitalization

iDesign - Providing the advanced IC Design market access to high-value information and essential tools.

Group Forms FD-SOI Project by Mark LaPedus
(iDesign Subscribers )
GlobalFoundries, ST to provide fabs for technology

Integrating sensor data acquisition in mobile... by Manuel Mota, Technical Marketing Manager for Analog IP, Synopsys, Inc.
(iDesign Subscribers )

Firms Lower Chip Forecasts by Mark LaPedus
(iDesign Subscribers )
Mixed signals seen in the market

Intel Takes On ARM With 22nm Atom by Mark LaPedus
(iDesign Subscribers )
Chip giant also bolsters security software line

More iDesign Articles >>

• GigOptix-40G DQPSK Demonstration

  GigOptix demonstrates 40G DQPSK with revolutionary TFPS polymer modulator

• Cost-Effective Millimeter Signal Analysis Approaches | Agilent Technologies

  This video was provided by IEEE.tv's coverage of IMS 2012 in Montreal. Material was created by Ben Zarlingo and presented by Bruce Erickson of Agilent Technologies. http://www.agilent.com/find/sa

• SDC Management and Verification: What's Missing?

  Sarath Kirihennedige, Sr. Manager Product Engineering at Real Intent, speaks with Graham Bell about how design constraints (SDC) are currently developed, what are the problems with the current approach and what a complete Constraints management and verification solutions looks like.

• John Blyler Interview on ChipEstimate.TV

  Sean O'Kane, Producer/Host ChipEstimate.TV interviews: John Blyler, Editor-in-Chief, Chip Design

• Synopsys Discusses its New DDR4 Memory Interface IP

  Sean O'Kane from ChipEstimate.com interviews Navraj Nandra about the Synopsys' DesignWare DDR4 IP product release. They discuss DDR4 SDRAM, its market, and their predictions for DRAM.

  Navraj Nandra, Synopsys and Sean O'Kane, ChipEstimate.com

• IMS 2012 Keynote on Integrating Design and Test

  Dr. Mark Pierpoint delivers the IMS2012 MicroApps Keynote address: As global competition increases, the need to produce the next state-of-the-art product faster has driven changes in how EDA and test instrumentation work together. Gone are the days when a design could be thrown over the wall to production. The next generation of communications protocols have barely been labeled "standards" when products using them have hit the streets. To produce better communications products faster requires that the line between EDA and test be blurred and new synergies between them created...

• Paul Estrada discusses the benefits of integrated analog FastSPICE with Tanner EDA tool suite

  Paul Estrada - CTO of Berkeley Design Automation - shares his perspectives on the benefits to users by integrating BDA Analog FastSPICE within the analog mixed-signal design tools offered by Tanner EDA.

more videos >>

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• Multicore Madness
  Are four cores really better than two for smartphones?
• Inside the Package
  What is the future of packaging, stacked die, and package-on-package?
• Changes In The Supply Chain
  Changes are accelerating as the industry pushes to the next process nodes and into stacked die.
• Architectural Changes Ahead
  New approaches are now required for improved battery life.

More Focus Reports >>

• EdXact: Bringing Innovation Into The Verification Flow

• InCyte

• Semiconductor Technologies > IP--Core - PLL and DLL Hard Macros

• Platform Express

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• Thinking Differently About Power
• Semiconductor Engineers Need Strong Technical and Emotional IQs
• Tackling the Challenge of Building Smaller, Lighter, and More Efficient Component-based Avionics with CFD
• The Current State Of Model-Driven Engineering

More commentary >>

• SmartFusion2 Lowest Power FPGAs

• Kintex 7 FPGA family: High Performance DDR3 memory throughput achieved by optimization of the memory controller

• Write Assist in Low-Voltage SRAMs

• Enea Element®: Simplify Distributed Systems with Frameworks from Enea Element

• Redefining RF and Microwave Instrumentation Through Open Software and Modular Hardware

• VPX for High-Performance Avionic Computers

More White Papers >>

• Inside Leti’s Litho Lab
• Trickle Down Equipment Economics
• 3D NAND Market Heats Up
• Editor's View: A July Chill, Again
• Semico Spin: Painting By Numbers

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• Experts At The Table: Latency
• First Silicon At 14nm
• Tradeoffs On The Fly
• Editor's Note: Big Iron Conundrums
• Absolute Power: Does My Phone Dream?

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• Executive Outlook
• What’s Ahead For System-Level Design
• Adventures In Verification
• Editor's Note: The Next Big Thing
• ESL Edge: Simple Economics

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• Chip Design Resource Catalog
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• Interoperability Guides
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• IP Solutions Resource Catalog
• Valuable Resources
  • AdvancedTCA
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  • FPGA and CPLD Resource Catalog
  • MIPS ® Embedded Resource Catalog
  • Multicore
  • PCI Express

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