Veloce Power Application Enables Mentor/Ansys Collaboration Gabe Moretti, Senior Editor One of the most interesting sessions for me at DAC was the luncheon that described the collaboratio...

Improved Power Management with Sonics' ICE-Grain Compared to conventional, software controlled approaches, Sonics' fine-grain hardware-controlled state transitions enable the architecture to exploit many more "off" an...

The Quest for Low Power Lowering power consumption requires a holistic approach that touches every aspect of the design, from the transistors to the standard-cell building blocks, to the circuit architecture, and going all the way up to the applicatio...

DAC Panel: Design Specialists Must Collaborate on Complex SoCs A disgruntled designer of analog chips became the focal point of a Design Automation Conference panel session during lunchtime Wednesday...

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Blogs

Gabe's EDA

Veloce Power Application Enables Mentor/Ansys Collaboration
blogger

Gabe Moretti, Senior Editor One of the most interesting sessions for me at DAC was the luncheon that described the...

The Internet of Things

Making the 8051 Secure from Hacking in the Smart Home Internet of Things
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By Jonah McLeod, Silicon Valley Blogger Jauher Zaidi, Chairman and Chief Innovation Officer of Palmchip Corp. based in...

The Canonical Hamiltonian

Part II: The Ecstasy and the Agony of UVM Abstraction and Encapsulation Featuring the AMIQ APB VIP
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Part II of our tour through UVM reusability through TLM ports and the factory in the AMIQ APB VIP. by Hamilton Carter...

JB's Circuit

Is Hardware Really That Much Different From Software
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When can hardware be considered as software? Are software flows less complex? Why are hardware tools less up-to-date? Experts...

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Datasheet Directory

    EDA Tools

    Verification Functional

  • by AMIQ EDA

    Design and Verification Tools (DVT) is an integrated development environment (IDE) for the e language, SystemVerilog, Verilog, and VHDL. It helps design and verification engineers...

  • by AMIQ EDA

    Thorough audit of your test benches Verissimo SystemVerilog Testbench Linter is a static code analysis tool that allows engineers to perform a thorough audit of their testbenches....

  • Methods / EDA Tools

    Design-for-Test (DFT)

  • by Source III, Inc.

    Source III provides the industry’s most comprehensive and cost-effective vector translation product (VTRAN®) which links simulation/ATPG vector data to ATE, a powerful vector...

  • by Source III, Inc.

    With nearly 25 years of field-proven success, VTRAN™ offers the most cost-effective, full-feature solution to creating EDA and ATE test programs from simulation and ATPG vectors....

  • Verification

  • by Agnisys

    IDesignSpec™is an award winning Electronic Design Automation tool that allows an IP, SoC, or System Designer to create the register map specification once and automatically...

  • by Agnisys

    IDesignSpec™ is an award winning Electronic Design Automation tool that allows an IP, SoC, or System Designer to create the register map specification once and automatically...

  • by Real Intent

    Meridian CDC is the fastest, highest capacity and most precise clock domain crossing (CDC) solution in the market. It performs comprehensive structural and functional analysis...

  • by Sutherland HDL, Inc

    Founded in 1992, Sutherland HDL has trained thousands of engineers throughout the world on Verilog, SystemVerilog, SVA and UVM. WORKSHOP HIGHLIGHTS Verilog and SystemVerilog...

  • Semiconductor Technologies

    IP - Core

  • by Calypto Design Systems

    Accelerate Time to Rtl, Reduce Verification Effort
    The Catapult® high-level synthesis tool empowers designers to use industry standard ANSI C++ and SystemC to describe functional intent, and move up to a more productive abstraction level.

  • by Calypto Design Systems

    With the explosion of consumer electronics, designing for low-power has become an important design constraint and a key differentiating factor. The RTL design phase provides the ideal opportunity to dramatically reduce power, since several micro-architectural transformations can be done at this stage, both via automated tools as well as manually by the RTL designers.

  • by Calypto Design Systems

    The emergence of consumer electronics is causing a fundamental shift in Register Transfer Level (RTL) design methodologies. The race for time to market has resulted in the adoption and growth of higher level design creation methodologies. In particular, High Level Synthesis (HLS) directly from software models to hardware has become very popular.

  • by Mixel, Inc.

    Organizations: GSA, MIPI Alliance The MXL-M-PHY-MIPI is a high-frequency low-power, low-cost, Physical Layer IP compliant with the MIPI® Alliance Specification for M-PHY®....

  • by SmartDV Technologies India Private Limited

    Organizations: EDAC, GSA, EIC, OCP-IP, Si2, SPIRIT SmartDV offers wide range of Verification IP’s, Memory models and Design IP’s. Verification models include complete...

  • by True Circuits Inc.

    Organizations: GSA The TCI DDR 4/3 PHY is a high-performance, scalable system using a radically new architecture that continuously and automatically adjusts each pin individually,...

  • by True Circuits Inc.

    Organizations: GSA True Circuits’ complete family of standardized, silicon-proven, low-jitter PLL and DLL hard macros spans nearly all performance points and features typically...



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