Josh Lee sees maturity in the services niche
Enormous attention is being focused on energy efficiency in mobile devices because time between charges trumps a slight boost...
DAC is in Austin this year, and I'll be headed over from College Station to check out the latest and greatest in functional...
When designing a system on a chip (SoC) that employs one or more embedded processor cores, the choice of available...
In Part II, IP Extreme's Savage reveals why IP standards take so long while discussing brand values, macro trends, and...
Docea Power, the design for low power company that delivers software solutions for power and thermal analysis at the architectural level , will exhibit at the 50 th Design Automation
With the explosion of consumer electronics, designing for low-power has become an important design constraint and a key differentiating factor. The RTL design phase provides the ideal opportunity to dramatically reduce power, since several micro-architectural transformations can be done at this stage, both via automated tools as well as manually by the RTL designers. more
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GigOptix demonstrates 40G DQPSK with revolutionary TFPS polymer modulator
This video was provided by IEEE.tv's coverage of IMS 2012 in Montreal. Material was created by Ben Zarlingo and presented by Bruce Erickson of Agilent Technologies. http://www.agilent.com/find/sa
Sarath Kirihennedige, Sr. Manager Product Engineering at Real Intent, speaks with Graham Bell about how design constraints (SDC) are currently developed, what are the problems with the current approach and what a complete Constraints management and verification solutions looks like.
Sean O'Kane, Producer/Host ChipEstimate.TV interviews: John Blyler, Editor-in-Chief, Chip Design
Sean O'Kane from ChipEstimate.com interviews Navraj Nandra about the Synopsys' DesignWare DDR4 IP product release. They discuss DDR4 SDRAM, its market, and their predictions for DRAM.
Navraj Nandra, Synopsys and Sean O'Kane, ChipEstimate.com
Dr. Mark Pierpoint delivers the IMS2012 MicroApps Keynote address: As global competition increases, the need to produce the next state-of-the-art product faster has driven changes in how EDA and test instrumentation work together. Gone are the days when a design could be thrown over the wall to production. The next generation of communications protocols have barely been labeled "standards" when products using them have hit the streets. To produce better communications products faster requires that the line between EDA and test be blurred and new synergies between them created...
Paul Estrada - CTO of Berkeley Design Automation - shares his perspectives on the benefits to users by integrating BDA Analog FastSPICE within the analog mixed-signal design tools offered by Tanner EDA.
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Frankfurt, Germany June 4-5, 2013
Austin, TX June 2-6, 2013
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Denver, CO June 18th, 2013
San Francisco, CA July 9-11, 2013
Nuremberg, Germany October 6-11, 2013