Solid State Watch: January 23-29, 2015 Solid growth in automotive semiconductor market; $4M grant to UMass Lowell for printed and flexible electronics development; Book-to-bill ratio belo...
The Various Faces of IP Modeling Providing all the needed types of models to successfully integrate an IP component into an advanced SoC is more comple...
Gabe Moretti, Senior Editor A little over a month ago I wrote a blog about eSilicon's IP MarketPlace. On Wednesday...
By: Jonah McLeod, Silicon Valley Blogger There's incredible hype surrounding the wearable market and most of it is aimed...
When can hardware be considered as software? Are software flows less complex? Why are hardware tools less up-to-date? Experts...
The holiday season is once again upon us, and, as usual this time of year, my thoughts are running to stories of science...
Design and Verification Tools (DVT) is an integrated development environment (IDE) for the e language, SystemVerilog, Verilog, and VHDL. It helps design and verification eng
Thorough audit of your test benches Verissimo SystemVerilog Testbench Linter is a static code analysis tool that allows engineers to perform a thorough audit of their test
With nearly 25 years of field-proven success, VTRANâ„˘ offers the most cost-effective, full-feature solution to creating EDA and ATE test programs from simulation and ATPG ve
IDesignSpecâ„˘is an award winning Electronic Design Automation tool that allows an IP, SoC, or System Designer to create the register map specification once and automatically
IDesignSpecâ„˘ is an award winning Electronic Design Automation tool that allows an IP, SoC, or System Designer to create the register map specification once and automaticall
Meridian CDC is the fastest, highest capacity and most precise clock domain crossing (CDC) solution in the market. It performs comprehensive structural and functional analysi
Founded in 1992, Sutherland HDL has trained thousands of engineers throughout the world on Verilog, SystemVerilog, SVA and UVM. WORKSHOP HIGHLIGHTS Verilog and System
Accelerate Time to Rtl, Reduce Verification Effort
The CatapultÂ® high-level synthesis tool empowers designers to use industry standard ANSI C++ and SystemC to describe functional intent, and move up to a more productive abstraction level.
With the explosion of consumer electronics, designing for low-power has become an important design constraint and a key differentiating factor. The RTL design phase provides the ideal opportunity to dramatically reduce power, since several micro-architectural transformations can be done at this stage, both via automated tools as well as manually by the RTL designers.
The emergence of consumer electronics is causing a fundamental shift in Register Transfer Level (RTL) design methodologies. The race for time to market has resulted in the adoption and growth of higher level design creation methodologies. In particular, High Level Synthesis (HLS) directly from software models to hardware has become very popular.
Organizations: GSA, MIPI Alliance The MXL-M-PHY-MIPI is a high-frequency low-power, low-cost, Physical Layer IP compliant with the MIPIÂ® Alliance Specification for M-PHYÂ
Organizations: EDAC, GSA, EIC, OCP-IP, Si2, SPIRIT SmartDV offers wide range of Verification IPâ€™s, Memory models and Design IPâ€™s. Verification models include complete
Organizations: GSA The TCI DDR 4/3 PHY is a high-performance, scalable system using a radically new architecture that continuously and automatically adjusts each pin indiv
Organizations: GSA True Circuitsâ€™ complete family of standardized, silicon-proven, low-jitter PLL and DLL hard macros spans nearly all performance points and features typi
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