Collaborative Advantage

Developing industry standards can be tough business. Getting them successfully, broadly adopted can be even harder. To re-purpose a very old phrase for EDA standards, “Many are called, but few are chosen”. To be sure, sometimes a few engineers can hit the bullseye defining a standard for the entire industry in their first try. Or, every so often an existing proprietary file format or language might get donated, stamped “approved”, and be welcomed by all competitors without a fuss. However, one well-respected IEEE standards leader estimated that 3/4 of all standards fail to achieve broad adoption after being approved. That seems like a lot of wasted effort. I get approached from time to time by Board members at other electronics industry consortia who want to know how Si2 measures effectiveness and performance. So, I’ll use today’s blog to share that information with all of you.

Si2 uses a set of annual metrics to assess performance and reward success. When I came on board in 2002, I setup a structured approach using a spreadsheet of priority-weighted categories and items that all multiply and add up to 100%. There are four top-level categories of metrics:
1. Adoption
2. Relevance and Influence
3. Engineering Execution
4. Fiscal Health
The largest priority weight is placed on adoption, which is the point when the ROI from the members’ investment finally gets realized. Relevance is about focusing on the most needed problems, and at the right time. Influence is about having the membership and marketing clout required to successfully drive the needed changes to succeed in our mission. Engineering execution ensures that the working groups are properly managed, and that delivery dates are met for the standards and any adoption aids (including software, libraries, test cases, and training). Si2 also performs an annual engineering satisfaction survey in which the results serve as a useful metric. Fiscal health keeps a check on our retained equity (“fund balance”), but also tracks forward-looking cash flow headroom. Adoption can be the trickiest to measure, especially when most efforts span multiple years, but there are indirect leading indicators that can serve as reasonable proxies even when full commercial adoption is at a later phase.

Within each category, several specific metric items are defined along with a priority weighting. We create three success scenarios for each item. The main goal counts for 100%, while partial success counts 50%, and achieving a challenging stretch goal counts for 125%.

These metrics are jointly defined at the beginning of each year with input from my staff and our members, then revised and approved by Si2’s Board of Directors. During the year, I review our progress monthly with my team during staff meetings, and we discuss ways to “unblock” barriers for the more problematic metric items. Each January, the prior year’s achieved results are then reviewed by the Board, and a final Organizational Metrics % figure is approved. That number directly affects the variable pay component for everyone at Si2, providing a strong incentive to succeed in all four categories. The higher the level, the more the variable component plays in the compensation. This is how it should be, to keep everyone focused on success toward our mission and priorities.

Having such structured, schedule-oriented metrics for developing and delivering standards may seem out of place at first, where we often start with a less-than-complete vision for an industry solution, use primarily volunteer resources, navigate through complex technical, business, and market dependencies, and all within a small non-profit organization. However, while Si2 may not be part of the for-profit, competitive products business, our members are. So, we must find creative ways to deliver and satisfy their real-world needs, within the schedule requirements they set for us.

It seems to me that a structured approach to assessing performance and adoption metrics ought to be a part of the Board-level accountability process for every standards development organization as a best practice. While no metrics are perfect, I can assure you that this system is highly effective at identifying where change is needed, and quickly motivating creative solutions.

Many readers may be unaware of a new standard coming out of Si2’s DFM Coalition early next year — one that I have yet to mention before now, but one that has significant potential benefits across the supply chain. So, I will use this blog to introduce OPEX — the Open Parameters for EXtraction. Someone suggested OPEX could also be an acronym for ‘OPerational EXcellence’, and here’s why.

OPEX was created to address the growing risk that has already cost the industry in terms of failing chips, with multi-million dollar price tags, and even worse a significant impact on tape out schedules due to re-spins. The root problems include:

1. the inability to confirm the validity of process parameter changes and ECOs across disparate design teams scattered around the world, across varying design flows using different tools;
2. the inability to confirm the validity of derived process parameter data against the master source data;
3. a lack of synchronization to changes in EDA vendor parasitic formats that are required to keep up with advancing foundry processes, making the mapping between the formats difficult and error prone (these commercial format changes may occur several times each year);
4. no existing semantic standard for naming conventions, ranges and units, or for process parameters or inter-parameter relationships, leading to more confusion;
5. errors existing in translation among parasitic formats and difficulty in managing the maintenance of various translators (which are often not lossless)

To manage these growing risks, companies have resorted to using multiple experts to review details of how to map process parameter names, units, ranges, and relationships, and maintaining wasteful conversion utilities and regression suites, and also hire consultants and perform business process audits to find, repair, and improve change procedures involved with process parameters after costly chip failures. It’s not a pretty picture.

The DFMC member companies have defined a solution to this problem with OPEX:

1. “Input Once, Use Many” — the master “Golden Source” process parameter data must be open, unambiguous, and comprehensive, easy to encrypt, track, control, distribute, and access across both commercial tools and in-house utilities, and easy to access / use over the internet (“in the cloud”).
2. “Golden Structure” for all process parameter data — based on XML with XSD structured templates, it can auto-verify compliance to naming, units, ranges, and relationships upon data entry or conversion.
3. Provably-Correct Export to SQL, UML, Excel — OPEX is more than a “file format”, it is an open XML/XSD database schema complete with verification routines and format translation support through integration with XML editors, SQLite databases, multiple scripting languages, and MS-Excel.
4. Data Visualization — Using 2D and 3D graphing features of Excel, process parameter data can be easily viewed to find corner cases that design teams wish to avoid that may affect performance or yield.
5. Ensure Interoperability — OPEX has been created to be fully compatible and bi-directionally lossless, based upon the generous contributions of ITF, ICT, and MIPT from EDA leaders Synopsys, Cadence, and Mentor Graphics, respectively. OPEX does not compete with any existing parasitic format, it complements them with an open, standard database and enhances their value with design teams. This is analogous with how the LEF/DEF format complements, but does not compete with, the OpenAccess database.

OPEX has already been used in its “pre-release” state by several DFMC members on production chips because it is so complementary, and has been verified as lossless alongside vendor formats. DFMC members are also working with the Synopsys IMTAB, which advises on changes to the ITF format, to keep everything in-sync. OPEX is really an open XML / XSD standard, with data populated and manipulated using SQLite, scripts, MS-Excel analysis, XML editors, and import/export with commercial EDA formats.

Solutions like OPEX have great practical value because they truly represent a huge potential for cost / time savings, and are entirely complementary with current practice. If you are interested in learning more about OPEX and how you can start putting it to use, please contact Si2 — or one of the OPEX WG members.

Chip design teams are all pretty well trained by now to equate “IP” with a block of design content, either “soft” or “hard”, licensed from some external supplier, leveraged to improve design reuse and time-to-market. However, this blog isn’t about that. It’s about managing the “other” kind of IP… actually the original, broader legal interpretation of “intellectual property”, as in patented works. Specifically, I’m talking about the role of managing patents in the world of standards. It’s not what you worry about every day, but that’s why I’m writing this — to share a few core principles you really ought to understand if you develop, contribute, or even use standards in your work.

In EDA, we used to create simple “file format” standards with little regard to patents – after all, what could possibly be patentable in a file filled with “Parameter == <value>” statements? Yet over time, much more sophisticated standards would emerge, closely correlating to much more valuable concepts and clever implementations as we kept advancing toward 20nm silicon techniques. Furthermore, many standards today routinely include software source code IP. These risks became real with consortium-related lawsuits over RAMBUS and SCO Unix, and legal departments now had to worry about the origins of contributed technology, the risks of adopting it, and the risks of sharing what they had if it related too closely to patented techniques.

For standards bodies, there are two broad categories of risk I’ll discuss:
1. The legal risk to a participating company’s own IP portfolio, and
2. The financial risk to using a standard that may contain hidden, latent licensing surprises.
The main idea behind the first risk, protecting the member’s IP portfolio, is to ensure that contributions of IP are always voluntary and explicit. There should be clear, written procedures for offering IP to (or excluding IP from) the group developing the standard. You should make sure that the standards group’s processes ensure that typical technical discussions or slide presentations among peers do not trigger an involuntary “contribution” of IP.

The central idea to avoiding nasty royalty surprises after adopting a standard, is to ensure a transparent, legally binding development process. This means that if any member of the group developing the standard has direct knowledge of IP in their company that might be necessary to adopt the standard, they must either exclude that IP in a certificate attached to the draft specification before voting, or be be legally committed to offer “RAND” licensing terms to all requesters, if the issue arises later. After the standard is published, a “reciprocal RAND licensing” clause then adds growing safety as other companies adopt the standard more broadly across industry. Essentially, each company accepting the license terms for that standard agrees to offer similar RAND terms to all others who developed the standard and/or accepted the license.

Si2 worked this all out 5-6 years ago with a thorough “IP Policy” that implements the above ideas. If you hear about a “60 day exclusionary period”, that just means that the standard is considered done, but is not yet published so any member has time to review and submit a RAND License certificate or Exclusion Certificate on that specification (if they so choose). The resulting standard can then be adopted as safely as possible, across industry, for years and years to come.

In case you missed it, GLOBALFOUNDRIES last week announced at Si2Con that they are contributing the full set of DRC+ data structures to Si2, to be integrated into Si2’s OpenDFM standard, which is developed and maintained by the DFM Coalition (DFMC). You can read the press release here: http://www.businesswire.com/news/home/20111020005541/en/Si2-Announces-Donation-DRC-GLOBALFOUNDRIES.

I actually have little need to explain the technical or business benefits of DRC+ pattern-matching technology. Fellow (professional) blogger Richard Goering has already done a truly fine job of that (see: http://www.cadence.com/Community/blogs/ii/archive/2011/10/23/globalfoundries-drc-donation-new-era-for-dfm-standards.aspx). Instead, I’ll add my own perspectives on what this donation means in DFM Verification to chip designers and EDA / foundry partners.

First of all, DRC+ utilizes innovative (and award-winning) pattern-matching technology, it can run highly accurate design checks by orders of hundreds to thousands of times faster than typical model-based simulation, which saves valuable company time and resources near chip tapeout. Second, it can improve designs by going beyond “pass/fail” to identify yield-detracting patterns and recommending more robust ones. Third, EDA tools can flag patterns for automatic yield improvement, making it useful for chip design teams before tapeout. Of course, the classes of problematic patterns must be identified first – and Cadence supported the development of DRC+ with a pattern classification tool to do just that.

What is so important about this announcement for the industry at large? To begin with, GLOBALFOUNDRIES’ generous decision to contribute this new, leading-edge innovation to the DFMC means that the entire industry ecosystem can benefit from DRC+ as an open industry standard. Not only will it now be an open standard, but it will be deeply integrated into the larger OpenDFM standard. All of the benefits of OpenDFM and all the benefits of DRC+ will come together, which is how the industry wants to see it.

DRC+ and OpenDFM are dynamic, living technologies, just as our design methodologies and process technologies are dynamic — constantly evolving with time and experience. So it is critical that the standard be managed as a truely collaborative effort, where no one company’s interest can stall or override the interest of other companies. It is also important that there be sufficient resources to evolve the standard rapidly according to industry’s changing needs (OpenDFM just had two releases in less than 1 year).

These new technologies are not sufficient as standards specifications alone: what makes them valuable is customer adoption support. This is the “real” stuff you need – such as XSD/XML DRC+ patterns, OpenDFM parser, design test cases, sample libraries, training / tutorials, etc. The DFMC is well-equipped to handle those needs, and do so in a strictly non-discriminatory fashion.

Overall, the ultimate value of the DRC+ donation by GLOBALFOUNDRIES means that the entire industry will enhance it’s capability by virtue of working together. That is the true essence of the title of this blog (“Collaborative Advantage”), and also Si2’s tagline: “Innovation Through Collaboration”. Please consider participating along with these other leaders of industry, to help make it even better.

DRC+ is a technology that happens only once or twice in a decade. It compresses days into hours and hours into minutes to improve yield without sacrificing accuracy. At Si2, we are proud to guide its development and provide its benefits to the semiconductor industry.

In case you didn’t already know, the 16th Si2-hosted conference highlighting industry progress in design flow interoperability comes to Silicon Valley (Santa Clara, CA) on October 20th. Si2Con will showcase recent progress of our members in the critical areas of:
1. Design tool flow integration (OpenAccess);
2. DRC / DFM / Parasitics interoperability (OpenDFM and OPEX);
3. Low power design (CPF. low power modeling, and CPF/UPF interoperability); and
4. Interoperable Process Design Kits (OpenPDK)
Si2 is also ramping up a brand new effort to define standards for 3D / 2.5D design of stacked die (Open3D), and this event will be an excellent opportunity to meet with Si2 and members who will be present to find out more about it. To learn more about Si2Con and register for this exciting event, go to: http://www.si2.org/?page=1490.

While I could next delve into the keynote talks and session contents, I’d rather use this opportunity to share our thinking on the event’s change in name and other behind-the-scenes aspects. Let’s begin with the name change!

Back in the early 2000’s, Si2 began hosting workshops around the new OpenAccess vision and technology, with the goal of helping advance OpenAccess adoption through sharing of requirements, experiences, technical knowledge, and broadening the interest and participation in it’s guidance and development as a true community effort. These workshops grew into the “OpenAccess Conference”, which was successful – so much so that we even doubled them to twice per year during the helter-skelter years of rapid changes and initial adoptions around the industry.

Once Si2 proved to be good stewards of OpenAccess (and LEF/DEF), our members brought us into an emerging area of need with the DFM Coalition, which also was covered in a parallel track at the OpenAccess Conference. A similar pattern repeated itself with the Open Modeling Coalition, Liberty TAB, and Low Power Coalition as well. By the time we began covering progress from the LPC in 2006, we began expanding the name slightly to “OpenAccess+ Conference”. Last year, we hinted at the broader scope of coverage with the name “Si2/OpenAccess+ Conference”, to get industry used to associating the long-familiar “OA Conference” with this broader name. All of these were interim, incremental transitions in brand management toward the final “Si2 Conference” name to reflect the full scope of coverage.

As press time drew near, we started thinking about keeping the event name short and simple, one that might lend itself to a logo. Si2 is definitely an engineering-centric organization, so logos were never very important in those early years, but as Si2 expands it’s breadth of membership across the supply chain, it becomes more important to establish a visual identity. Hence, we have begun this process by dubbing the event simply “Si2Con”, and creating a basic logo to match. We are interested in more creative name and logo ideas – we are even planning a “conference naming contest” ahead (so Watch This Space).

Why does Si2 pull together this annual conference? It’s very simple: our non-profit mission is to promote interoperability, improve efficiency, and reduce costs through enabling standards technologies – and these technologies are only valuable to the extent they are broadly adopted and used. That means bringing the right experts together on a topic to share technical challenges, educate industry peers on these new solutions, and share adoption experiences. Enthusiastic attendees tell us that one of the main benefits is networking with same-domain technical peers, listening to a wide variety of presenters that take a “flow” perspective as they do, and ability to see live demos of interoperability progress in action.

As always, an excellent luncheon will be provided, sponsored by Cadence Design Systems.

Please consider joining us at ‘Si2Con’ and see for yourself!

Lately, there has been increasing discussion in the industry about the need for a set of standards that specifically support interoperable description of intent for analog and custom design, a.k.a. “analog design intent” standards. It is a big, complex, and intriguing topic, with multiple valid points of view representing different aspects of the supply chain. Most concede that it consists of a set of specifications, some being extensions of existing standards, supplemented by several new ones. With the analog and custom IC product landscape increasing with a large consumer / mobile market, and the potential for increased tool automation also of growing interest by EDA vendors, it is hardly surprising that the topic has transitioned to more actionable, tangible calls for action in the standardization space.

Proponents calling for analog design intent standardization point to the rising percentage of effort in handling non-digital design and layout tasks, made worse by technology changes due to advanced process nodes. While digital enjoys formal executable models, automated synthesis, and top-down constraint specifications, the analog world relies on exchange of datasheets, manual topology selection and sizing, and less automated place and route and verification. Some reason that the relative gap in automaton is largely due to the lack of formalism in description of intent and the lack of commonality preventing the various “views” to be exchanged between tools across a design flow. Open standard interfaces could permit far greater exchange of analog intent, with greater formalism and clarity, to greatly improve time-to-market, quality, and efficiency for the industry as a whole.

Those who are less eager for such standardization argue that some of that information is really the result of proprietary IP investments made over many years, and the resulting methodology used with those tools reflects as much the internal product-level details as it does more generic description of intent. The point has also been made that the goal may be more about pricing leverage than about innovation in analog design intent.

Si2, playing such a prominent role in related standards such as OpenAccess, OpenPDK, and OpenDFM, is indeed the logical place for such a conversation, and those efforts cited were in fact created in response to similar requests from our members and industry at large. At this time, Si2 is seeking serious, qualified input from those who are stakeholders in this arena, and we have no formal position either way. As with our past efforts, Si2’s response will be rooted in careful analysis of the breadth of industry need, the potential for widespread benefit and ROI to outweigh likely cost / effort, ability to leverage existing standards and technologies, legal constraints, and the expectation of active participation and contributions to help the adoption of the investment succeed. With five major active efforts at Si2, including the ramp-up of Open3D taking place as we speak, we are not looking for more work! However, we do have the ability to scale, only if needed, to address important challenges within Si2’s scope.

So, please share your thoughts with us on this topic. Si2 will listen carefully — to our members, but also the broadest possible audience, the “engineering community” represented by readers of this blog. Feel free also to add comments below for more general feedback. Or better still, come see what’s going on at the 16th Si2 Conference on October 20 in Santa Clara: http://www.si2.org/?page=1384
Thank you!

Summer is a time for relaxing and recharging, at least for a bit. I took some time off (despite numerous comments about not updating my blog) to enjoy time off with family and good friends. This included an exciting trip, with a week of white-water rafting 87 miles through the Grand Canyon. One look above us at the nearly mile-high side walls of tiered rock and sandstone layers, as seen from the depths of the Colorado River below, gave new meaning to silicon stacking and vertical trenches!

We put in at Lees Ferry (near Marble Canyon, AZ) in a 4-passenger oar-driven raft and supplies for 6 days of food. Drinking water is generated with a solar panel to charge a battery that runs the 50 degree river water through several filters. The rapids ranged from class 3 up to class 5, and the rapidly melting ice water from Lake Powell moved the water at a brisk 26,000 cubic feet / second. We stopped for special sightseeing hikes several times per day, and camped under the stars. One time we had to swim through icy water, then algae-laden stagnant pools, climbing up a rope 30 feet, then wading through more muck to reach “The Silver Grotto”. We hiked up and down the mountain side to reach a “sideways waterfall” where we could swim and relax. Another time we hiked to the Little Colorado River, with surreal bright turquoise blue water (the product of calcium carbonate and copper sulfate minerals in the water); we were allowed to jump in to be carried away through its rapids.

Food was surprisingly good, as our guides prepared everything from steaks to cakes using LP gas. As we traversed downstream, the water’s altitude kept dropping at the same time as the walls of the Grand Canyon stretched up ever higher, until we reached our destination at Grand Canyon Village 6 days later. At that point, the water-to-peak height approaches one mile. After hiking our duffel bags to the mules at Phantom Ranch, we then began the 7.8-mile vertical hike to the top about 7:15am, reaching the top around 12:45 in the 100-degree AZ heat. Quite an adventure!

Along the way, I was amazed at the variety of rock formations clearly visible in the (mostly) horizontal layers dating back 1.8 billion years. Sometimes, violent forces from heat build up would literally melt and bend the rock layers from horizontal into a nearly vertical orientation. We sure wouldn’t want that to happen to stacked silicon dies, would we?
All Grand Canyon metaphors aside, our industry is indeed preparing to “go vertical” with mainstream production capability of 2.5 and 3D stacked die utilizing Through-Silicon-Vias (TSVs), and part of that is setting up the common infrastructure required, including design data standards. After a successful kickoff meeting at DAC last month, industry experts are now joining the “Open3D” TAB under the auspices of Si2. Every part of the semiconductor and EDA / IP supply chain was represented at the DAC meeting, and there are some pretty aggressive schedules including 1H of 2012. If you are interested in participating in Open3D, please contact Si2 for more details. Si2 is coordinating its Open3D activities with other key consortia, including GSA, SEMATECH, SRC, IMEC, and LETI.

I’ll follow up with more meat around Open3D in my next blog… but in the meantime, don’t forget to enjoy your summer!

In February, the Low Power Coalition (LPC) published their third release of the Common Power Format standard, with over 100 pages of (backward-compatible) enhanced capabilities including added CPF commands to enable greater compatibility with IEEE 1801. The LPC also created the CPF/UPF Interoperability Guide to relate commands in CPF and equivalent mapping to 1801-2009. Yet there are limitations to what can be mapped, notably with the older UPF 1.0 constructs.

Many industry-leading companies spanning fabless, IDM, IP, OEM, and EDA have underscored to Si2 the ongoing negative impact on productivity when trying to work with both CPF and UPF/1801-2009 in tool flows, despite best-effort command mapping. The root of the problem is deeper than syntax differences – it is about incompatible methodologies for how to organize and manage low power intent data. This became clear after recent customer visits in the U.S., Asia, and Europe, so Si2 chose to offer our help and leadership in resolving those gaps with a coordinated effort being called “OpenLPM” (LPM = Low Power Methodology).

OpenLPM is not a new standard or new project — it is a proactive approach by Si2 and our LPC members to resolve these productivity challenges by contributing certain CPF technology to the P1801 Working Group (WG). This allows the P1801 WG to enhance the capabilities and use cases (methodologies) in the 1801 specification for a smoother overall flow when working with both environments. Three primary features are required for a converged low-power methodology:
(a) Power-domain-centric organization of intent;
(b) Successive refinement of power intent detail; and
(c) Formal support of hierarchy for IP reuse.

Last week, Si2 and the LPC made a technology contribution of these features from CPF to the P1801 WG. It is Si2’s sincere hope that these will not only be helpful to improve the next revision of 1801 (targeted for 2012), but will also make major inroads in reducing the friction in working with multi-vendor tool flows. The next step will be for the P1801 WG to determine which portions of the Si2 contribution (if any) to accept for incorporation into the next revision of 1801. Si2 has been an active member of the P1801 WG and will continue to support the LPC charter to lead in low-power flows, independent of format.

A press release explaining additional details of OpenLPM and including quotes of support from many industry leaders can be found at: http://www.si2.org/?page=1348

The Design Automation Conference (DAC) is an annual ritual in the world of EDA and the electronics industry, and it remains the single largest venue for announcing progress in Si2 standards, sharing that progress in (free) technical workshops, demonstrating that progress in demos, and celebrating our collaborative successes together (as in face-to-face, an increasingly rare opportunity in this Internet age). In this blog I’ll quickly summarize “everything DAC” from an Si2 perspective. With nearly 100 corporate members, there’s a lot going on.

OpenDFM and OpenPDK Team Up: While the DFM and OpenPDK coalitions have definitely unique goals, scope, and membership, there are clearly areas where each set of standards can help the other set. Monday morning’s DAC Workshop is titled “Synergies in IC Design: PDK and DFM Standards Working Together” for good reason. This is a great opportunity to learn more about two very exciting areas at the same time. OpenDFM rules bridge the gap between a layout style that allows only a few, very restricted layout patterns and a style that allows purely arbitrary layouts. Second, there is ongoing effort to standardize a common format for representing parasitic information and to better handle manufacturing variability. This has implications in how this data is represented in PDKs and how they affect the modeling of design parameters for power, timing, and SI analysis. More detailed information is here: http://www.dac.com/workshops+_+colocated+events.aspx?event=47&topic=3

OpenAccess For Everyone! “It’s not just for programmers anymore”… The OpenAccess Scripting Language Workshop shows off this new framework infrastructure (based on SWIG) that enables a wide variety of popular scripting languages. Learn all about how to connect with OpenAccess using Tcl, Perl, Python, or Ruby, either integrated with native C++ code or as stand-alone programs. Engineers use scripting languages as part of their daily work. This tutorial will provide an invaluable knowledge base of what is available through programming examples created by Si2 as a complement to the popular C++ API tutorial. And very importantly..since we would have no speakers or attendees during the middle of the session, we have a built-in break so everyone can go see the “Woz”, Steve Wozinak’s, Keynote Address. For more information, see: http://www.dac.com/workshops+_+colocated+events.aspx?event=1&topic=8

You can return to the session, without missing anything, then stay in the same room for…..

Party With A Purpose: In celebration of over 23 years of service to the IC design industry, refreshments and light hors d’oeuvres will be served at the Annual Si2 Open Reception Monday afternoon. This reception is free and open to all who are interested in Si2 activities such as OpenAccess, DFM, low-power design, 3D ICs, and OpenPDKs. The keynote speaker will be Philippe Magarshack, Group Vice-President – Central R&D, STMicroelectronics. The title of his talk will be “The Value of Open Standards for Systems-on-Chips in 28nm and Below”. As always, I will also present a short summary of Si2, our exciting year’s accomplishments, and new directions ahead. This party will end in time for everyone to attend the nightly DAC Reception at 6PM.
For more information, see: http://www.dac.com/additional+meetings.aspx?event=64&topic=13

Three-Ring Circus at the Si2 Booth (#1631): It’s a busy place at this year’s Si2 booth, with 7 Si2 Members demonstrations of products that integrate Si2 standards and collaborative technology, including Analog Rails, IBM, Cadence, Magma, Mentor Graphics, Pulsic, and Synopsys. These companies will be showing how Si2 standards developed by the OpenAccess Coalition, the OpenPDK Coalition, the Low Power Coalition, the Open Modeling TAB and the Design for Manufacturability Coalition can provide innovative approaches to critical IC design flow issues.

The EDA industry has played a pivotal role in the semiconductor supply chain since it’s origins in the early eighties. Yet, nearly 30 years later, we have an important issue to work through as an industry. What’s at stake is nothing less than EDA’s fundamental role in supporting an evolving semiconductor industry over the next decade, not to mention what kind of standards will be required to support this ecosystem. Because “EDA360″ is now in our current vernacular, and so closely connected with these trends, I’ll address it as part of my industry analysis.

There is no need to repeat the unavoidable trends of the electronics industry and semiconductor’s role within it. The primary, sustainable value in electronics continues to migrate upstream above the silicon itself – it’s about the system, the application, the content, and the inter-connected infrastructure that delivers that content. In this era, the silicon that wins in the market will be the silicon that gets the most out of the software applications and neighboring hardware to realize that value potential. EDA’s role should be to enable that optimization of silicon within the context of the full product. Let’s dissect what that really means and why we’re not there yet.

Optimizing the myriad trade-offs of silicon features, performance, power, area, and cost are hard enough. However, when much of the feature set resides in the software stack (some of which is being designed in parallel), that job becomes much harder. It gets more difficult when other software components and other silicon components comes from other companies. And it becomes near impossible if the critical information needed to make signoff level analyses, estimates, and judgment calls is unavailable. In this context, more and more of the engineering team’s time is being focused outside of traditional EDA scope, because decisions about the system can only be made outside of EDA. This is not good for EDA’s perceived value-added role in building systems on a chip.

I am not making a case for getting EDA into the crowded, low-margin software development world, in fact quite the opposite. Rather, EDA’s deep silicon expertise uniquely qualifies it to take the lead in mapping what essential information from the software world must be passed into the “function / timing / power / noise / DFM” world, then using that to perform new and wonderful algorithms that guide the decision space for an optimal end product experience. EDA should want that focus and value happening within it’s tool flow, where it belongs. Bringing that value more visibly into EDA’s arena is the best way to deliver long-term growth.

If one were to ask the major EDA vendors “what is EDA360?”, there would clearly be a diversity of responses. Cadence, having issued a white paper describing the vision in pretty good depth, has defined a fairly clear answer to this question. I have also read articles from several other EDA executives and leading niche vendors, expounding the EDA360 concept and the need for a new EDA vision. A handful of other articles / blogs have focused on various aspects of EDA360, generally quite positive on the idea… but with a healthy dose of skepticism about either the motives of Cadence or the ability of this EDA industry to adapt. Other major EDA vendors appear to have kept a low profile, perhaps hoping it will just fade away.

Regardless of the company that coined “EDA360″, are the principles well aligned with the trends described above? If so, then what do we choose to do as a response? Some might argue that any proposal offered by a single EDA vendor would be met with identical skepticism by that vendor’s competition and thus cannot succeed. If that is true, then how does the EDA industry ever coordinate on a direction for it’s own future? Or, are we just making the conscious decision not to coordinate? There is little doubt in my mind that the system-view “value shift” is happening, and EDA will either be at the center of where these critical, intersecting trade-offs occur, or run the risk of being left off to the side.

I see an increasingly interconnected world, where economic business models are forcing greater collaboration and coordination to deal with intricate complexities. I see a vision of well-timed standards playing an increasing role to open up new market opportunities, allowing the industry to hit “economic critical mass” by lowering cost and improving efficiency.

So, if not “EDA360″, then what? What is our strategic alternate path to grow our collective vision? Can EDA change itself, or will it forever remain confined to the minor role it originally filled in the 80’s and early 90’s? Regardless of the label used, I believe the EDA industry is up to the task and wants to embrace a new major role in “next chapter” of growth. I’d like to hear your thoughts on how we get there.