Collaborative Advantage

“Models should be as simple as possible… but no simpler!”. Albert Einstein’s philosophy captures an eternal truth in modeling the physical world for any given purpose. Why? Because unneeded detail takes more effort to create, more CPU run time to execute, while too little detail for the task means a non-competitive product. Modeling is complex topic all by itself (I will discuss the broader topic in an upcoming blog about the conundrum of modeling in general, and the role of standardization). As it turns out, power modeling is a particularly tricky special case.

Recently, fellow blogger and professional journalist Ed Sperling wisely observed that “power is creating a whole new layer of issues”. Even worse than that, power intersects with function, timing, area, reliability, packaging, battery life, etc. Modeling of power is fundamentally a flow issue as well as tools that must accommodate the appropriate design constraints,not just about a file format.

Allow me to share some excellent work the Low-Power Coalition (LPC) leadership has been doing to advance power-aware design capability in the modeling arena. The LPC has identified four areas of work, which I will explain below:
1. Implementation (cell) level: Liberty model enhancements for power;
2. Design level: complex atomic events in transaction-level (TLM) power models;
3. System level: structural definition for electronic system-level (ESL) power models; and
4. Layering “power variability” onto the design flow.

Large IP blocks have many internal states, often composed of subcomponents, each with their own power states. Requiring mutually-exclusive states, as Liberty specifies, can cause exponential state explosion. In one LPC example, an IP block containing 6 different memory arrays, each with 3 (sleep, nap, active) power states could be described with 18 power states (3*6). Coding this in Liberty, however, would require 729 power states! So the LPC has begun discussions with the Liberty TAB to offer Liberty enhancements for non-mutually-exclusive states to resolve this problem.

Today, it is nearly impossible to accurately model IP blocks and complex functions for power without modeling all internal transitions and lower-level data. The need is to atomically model power consumption of complex IP blocks purely at the transaction level. One proposed solution would be a Liberty enhancement to define state tables allowing assignments of energy to state transitions, however there are several workable approaches to deliver an interoperable capability here.

Most ESL tools do not directly address power modeling, and those that do lack any form of interoperability. The common practice of filling spreadsheets to manage power has reached its limits in terms of capacity, descriptive richness, and efficiency. So, the LPC is working toward defining an interoperable, machine-processable abstract structure for ESL-level power models. Questions to be addressed include: What data objects are needed? How are they inter-related? How would tools utilize this data? How much detail / accuracy is necessary, and how difficult is it to populate that data? Creating interoperable ESL-level power models could help the industry reach much-needed critical mass in this domain.

“Variation-aware” design has been a topic in several Si2 projects over the last 5 years, starting with the Open Modeling Coalition for timing, followed by the DFM Coalition for process parameters. Now, the same trends are emerging as important considerations for managing power, too. Today there are no standards for handling power variation – but this can be essential to balance between design failures due to missing corner case extremes as well as to avoid sacrificing performance, capability or cost due to unnecessary over-design. The impact of variations – caused by inter-related logical, electrical, and physical factors – is not constrained to a single point in the design flow.

In defining new standards, especially in emerging areas, how does an industry body assure a thorough result of enduring value and quality? The answer is to use a thorough process and engage key thought leaders across industry. LPC members outlined an approach for how to properly go about defining a power modeling standard the entire industry can use. For example, every feature might be accompanied by work flow use cases, and supported by a range of test case designs that include both a “top-down” power model (user-created) and a “bottoms-up” model (such as generated from characterization data). The design abstraction levels might include TLM, untimed, cycle-accurate, RTL, and so on. Required application features might include average, peak, static IR drop, EM analysis, transient power grid analysis, and so on. As you can tell, power modeling is indeed a complex topic, and it will surely be phased in and enhanced over a period of many years.

The first fruit of this process was the Power Modeling Requirements v1.0 specification, released in May, and v1.1 is being readied for a 2H10 release. Multiple very active working groups are discussing, aligning, and defining a path these companies intend to follow to achieve practical, adopted standards to benefit their corporate needs (as well as industry at large). In addition, invited guests include noted authorities from the academic and research communities.

I encourage anyone who sees value in these low-power modeling efforts to join the effort, to help us and themselves as well as the existing LPC members in achieving these ambitious goals. New participants are always welcome on a strictly non-discriminatory basis. You and your company can benefit from exchanging leading technology insights with the domain experts from the LPC member companies, and you can directly influence upcoming standards in the power modeling arena.

I started my career as an EE designer nearly 30 yrs ago, coincident with the EDA industry’s Big Bang triumvirate of “Daisy-Mentor-Valid”. Things were so simple back then: CAD tools helped you capture a schematic, generate a netlist, and – with any luck – simulate a few thousand digital gates. Of course, for analog design, SPICE was the anchor – and 30 years later, little has changed!. Sure, every company had package experts, and thermal / stress experts, and CMOS process experts, but they were too-often hidden from the digital team behind closed walls.

Today, things are much more complex – and those old walls are now becoming inter-connected webs. Every discipline is interacting and cross-communicating, because failure to do so costs in schedule and performance. Floorplanning tools were a major advancement, the first time that the IC design team brought physical design details upstream. Soon after, “physical synthesis” tools blended the early physical and electrical disciplines together into communicating algorithms to improve timing and performance. This led to the “platform era” where an array of tools from a vendor became more tightly integrated together to design digital silicon (OpenAccess then contributed greatly to enabling multi-vendor integration). In recent years, these platforms have incorporated analog and digital design across the flow, including both early and late stages of design refinement. However, this will still not be sufficient for our next chapter of growth.

As the IC industry embraces “More Than Moore” challenges, it is clear that we must refresh our old paradigms in EDA – and likewise in EDA standards. For example, 3D stacked die is an important emerging area – including 3D circuits and 3D interconnect (TSVs). One can draw parallels with the early days of IC floorplanning (called “pathfinding” in 3D) and the trend for more tightly-interconnected algorithms across disciplines. We won’t get there in one step, and that’s fine – this market needs to develop, starting with “2.5-D”, then “2.9-D”, and so on. Yet over time we must integrate physical, electrical, thermal, mechanical, packaging, test, DFM, and reliability disciplines together. “Frontend” and “backend” cannot be used as simple labels for separation of concerns – since some abstraction of all aspects will be needed throughout the flow.

I can use a different example to bust our old paradigms: embedded software integration, and even application software integration (as in “EDA360″). Is it accurate to consider software design a “frontend” activity, or physical silicon design a “backend” activity? Just ask any software designer when his job is “done” and it is obvious that ongoing software / firmware updates continue well after the product has shipped (there isn’t much more “backend” than that!). The truth of the matter is that we must all interact across the entire design flow to create effective products to have any chance of satisfying performance, schedule, and cost requirements.

So, my appeal is for a fresh way of looking at EDA, and by logical consequence EDA standards. We must shed the old and outdated sequential “waterfall” paradigm, and embrace instead the modern “spiral” development paradigm of multi-discipline, inter-connected design refinement. In this way, we will have a much better chance to achieve our growth and efficiency objectives for our industry – from 3D to EDA360.

Successful standards are a reflection of changing business trends. For example, the success of OpenAccess was mainly due to growth in custom semiconductor design and data complexities when building flows to support custom design. As power, thermal, and battery life issues became the bottleneck in many consumer-era IC designs, the LPC and CPF/UPF standards emerged. The industry’s latest renewed focus on analog design automation in the inter-dependent fabless-foundry model drove the OpenPDK Coalition. Of course, I could also cite dozens of other examples all across the design flow – from Verilog to UVM – all reflecting needs and priorities of the times.

It’s not just standards that shift – even the basic business models have shifted dramatically. When the OpenAccess Coalition was formed 8 years ago, traditional IDMs drove the requirements and supplied the initial resources. Cadence soon joined in with an unprecedented resource commitment, but only because these IDMs set the vision and drove the agenda first. OpenAccess would not exist today were it not for the leadership and ongoing resource investment of these IDMs – even though in current times every part of the supply chain now benefits from OpenAccess, and it has enabled a wave of innovation on top of it that creates more opportunity for our industry’s success ahead.

This begs an important question: Who should be involved in developing standards? Eight years ago, the leading IDMs came together and “encouraged” their suppliers to engage with them, making OpenAccess possible. Today, however, many of those IDMs have gone fabless, and/or have shrunk in market clout to other fabless companies. These fabless design houses, along with their foundry and EDA partners, have quickly overtaken many traditional IDMs as the new market revenue leaders. Most of these newer fabless companies achieved their initial edge with a next-product “laser focus” that used available standards, but often minimized any investment in their creation or support. The problem is that the children have now become the parents, so to speak. Whose job is it now to invest in the future efficiency of our industry? Some industry observers claim that those who lead the industry in market revenues should also recognize that it is in their own best interest to take up the mantle and be leaders in standards development to enable a more efficient industry ahead.

Our industry has thrived through many dynamic transitions, and numerous significant EDA standards have been a key enabler for the industry’s success. Going forward, the new market leaders must continue to invest in those standards upon which we economically and strategically depend for our business, including those emerging areas where effective standards can enable healthy growth for our industry and competitive advantage for those who recognize that vision.

Having just returned from my 25th Design Automation Conference, there were a number of insights on industry trends that were brought into clearer focus, and I would like to share these thoughts with you today. Most DAC-blogs cover new products or which give-aways were the best, but I think I can add better value with a perspective to think about (and then discuss under the comments section).

While none are brand new or a surprise, there were several major themes I noticed coming out of this year’s DAC:
   * Blurring of roles across the supply chain
   * Foundry inter-dependence with EDA and standards
   * Analog / custom design focus
   * 3D is really coming

Blurring of roles across the supply chain: We saw evidence that the lines continue to blur between supply chain segments (EDA, IP, Foundry, and User). Both Virage Logic and Denali have merged into EDA, creating new opportunities (as well as new threats, no doubt… time will tell how this will help EDA revenue and market strategies). Foundry reference flows continue their advance further up the food chain to incorporate higher-level EDA, more IP, and more design flow standards. In PDKs, EDA, IP, and user companies are all “producers” of PDKs to varying extent, not just foundries. These shifts change the competitive landscape at every turn, so as a result old partnerships and competitive positions will be re-assessed as the market adapts and realigns to a new reality.

Foundry inter-dependence with EDA and standards: It was hard to miss the fact that GLOBALFOUNDRIES made a big splash at DAC this year – the CEO DAC Keynote, numerous sponsored events, a Sr. VP speech at Si2’s Open Reception, and more. TSMC continues to expand it’s DAC presence as well, and continues to demonstrate the growing inter-dependence of foundries with EDA and EDA standards in reference flows. DAC even released a special press announcement specifically about GLOBALFOUNDRIES, TSMC, TowerJazz, and The Common Platform. At Si2, we see growing inter-dependence of these and more foundries with Si2 standards (with more press releases coming, of course). The message from foundries is clear: prevent “garbage in, garbage out”. In other words, a good silicon manufacturing business depends heavily upon a healthy stream of good designs that utilize the investments foundries make.

Analog / custom design focus: The recent rise in competitive choice in analog EDA seems to be settling into real business decisions now, with some significant market impact and a sense that we are on the cusp of a sort of Renaissance in growth and fresh approaches. In the standards arena, there is ample support for this premise with the strong commitments to PDK standardization, namely iPDK, IPL, and OpenPDK (note: these are all on a complementary path where each has its own value proposition and they all serve to reinforce this trend). OpenPDK is up to 14 members now and still growing… it’s twice the size of OpenAccess Coalition when it was started. Speaking of OpenAccess, it has a record-high membership of 41 companies as another sign of this trend.

3D is really coming: 3D stacked die is many things to many people (kind of like DFM in the early days), so it’s hard to judge when and exactly how 3D design takes off in a major way. Sure, some leading companies use through-silicon-vias today, but it is relatively awkward and risky for mainstream growth. However, this DAC convinced me that, while we aren’t certain when the broader market is ready to dive in, it will happen. The range of discussions on 3D at DAC, the good attendance at them all, and even the level of standardization interest shows it will be important and is coming into focus. I’ll share my insight on how I think the 3D market might actually take off in a later blog, but this DAC proved that it will be significant for our industry.

There is much more to DAC than the above themes, but these were some key over-arching themes that caught my attention. Feel free to share more views in the comments section.

The Design Automation Conference (DAC) is an annual ritual in the world of EDA and the electronics industry, and it remains the single largest venue for announcing progress in Si2 standards, sharing that progress in (free) technical workshops, demonstrating that progress in demos, and celebrating our collaborative successes together (as in face-to-face, an increasingly rare opportunity in this Internet age). In this week’s blog I’ll quickly summarize “everything DAC” from an Si2 perspective. With nearly 100 corporate members, there’s a lot going on.

A New Era For DFM: If you care about DFM and yield (and who doesn’t these days?), then you will want to attend Si2’s free DFM Workshop (http://www2.dac.com/workshops+_+colocated+events.aspx?event=22&topic=3). The DFM workshop describes the tools and techniques used to recapture the lost opportunities in performance and power while building designs which are more robust to greater process variability, and the agenda will include speakers from: Cadence, GLOBALFOUNDRIES, Intel, IC Scope, Grid Simulation Technology, and North Carolina State.

Advancing PDKs: If you care about custom, analog, or library design using Process Design Kits (a very hot topic lately), then you will want to attend the free “Advances in Process Design Kits” Workshop
(http://www2.dac.com/workshops+_+colocated+events.aspx?event=91&topic=13). This workshop will introduce all of the aspects of PDKs and the presenters will describe the state of the art and make recommendations for future work in the following areas. Interoperable Schematic Symbols, Design Parameter Specification, Callback Specifications, Pcells, SPICE Sockets, Technology File enhancements, and Process Retargeting and Verification. The agenda will include speakers from Cadence, GLOBALFOUNDRIES, Intel, Mentor Graphics, Springsoft, and Si2.

22-Year Celebration: Tired after a long day of DAc’ing around? Si2 is offering an Open Reception Monday (before those evening events) for drinks light hors d’oeuvres (http://www.si2.org/?page=1192). We will also celebrate the milestone election of GLOBALFOUNDRIES to Si2’s Board of Directors with an invited speech from Dr. Mojy Chian, Senior Vice President, Design Services and Enablement at GLOBALFOUNDRIES. I will also present a quick summary of Si2, our exciting year’s accomplishments, and directions ahead.

Five-Ring Circus at the Si2 Booth (#502): It’s a busy place at this year’s Si2 booth, with 5 EDA vendor demonstrations of products that integrate Si2 standards and collaborative technology, including Anaglobe, Cadence, Magma, Pulsic, and Synopsys. These companies will be showing how Si2 standards developed by the OpenAccess Coalition, the Low Power Coalition, the Open Modeling Coalition and the Design for Manufacturability Coalition can provide innovative approaches to critical IC design flow issues. An introduction to the new OpenPDK Coalition will also be highlighted.

Public Announcements: In case you don’t read the news, you might have missed some of the 12 (yes, that’s right – twelve!) press releases published on Si2, our coalitions, and new deliverables in the weeks leading up to DAC. Some of the major ones include the TSMC / Mentor / Synopsys contribution of iDRC to Si2, the new CPF-UPF low-power interoperability guide, members joining the new OpenPDK Coalition and OpenAccess Coalition, and our newly-elected Board members for 2010-2011. Also, many vendors have announced commercial support of Si2’s standards in their product announcements, which we very much appreciate.

This past week, Si2 released a long-awaited press announcement that was met with various emails and phone calls offering words of “congratulations”, “thanks”, “big milestone”, and “this is a big _____ deal” (actually, I made that last one up, but that was the sentiment!). So what’s the “big deal” about TSMC, Mentor, and Synopsys contributing iDRC to Si2’s DFM Coalition? I’ll explain this in today’s blog.

To begin with, it’s important to realize that passing DRC is an absolute gate to chip production, and therefore company revenue… and that physical verification of today’s complex chips has become harder for multiple reasons. First of all, the chips have more transistors, more layers, and more routes than ever before. Second, many ICs are designed at advanced process nodes where the physical verification rules number in the thousands, with billions of features to be verified on each one. Third, an increasing number of these rules are now design context-dependent, with conditional rule checks and an explosion of DFM concerns that require much more processing to determine which rules apply where. Finally, as if this task weren’t hard enough, these complex and intricate rules often need to be written multiple times in different formats to support multiple EDA tools.

TSMC recognized this growing problem early, and took a leadership role to manage the increasing cost and schedule risks with the concept of a single “meta-language” named iDRC. Working with their EDA partners, TSMC invested in bringing iDRC into full production, and has been very successful with widespread adoption across the industry.

At about the same time, a group of companies under Si2 called the DFM Coalition (DFMC) had been working on physical DFM standards, and had defined nearly 250 DFM parameters ready for inclusion into a new standard. However, rather than create a separate file format for DFM, it was clear that layering standard DFM checks into a DRC language was a far better solution for industry. But how could this be done among the multiple proprietary DRC formats? Fortunately (for all of industry), iDRC was offered as a practical basis for creating an open standard under Si2, which is being called OpenDFM. The members of the DFMC’s Compatibility Working Group, along with Si2 staff, are presently ensuring 100% compatibility with iDRC as OpenDFDM is being readied for imminent release as an official Si2 standard. Because it is so important to get it right the first time, this assurance includes testing with actual EDA vendor tools.

Now, fast-forward to last week, where this contribution was publicly announced. For many in the industry, having an open standard (meaning shared ownership control and community-based evolution) is a huge step for physical DRC, a fundamental prerequisite to chip revenue. It would be very difficult to migrate to OpenDFM if it were not directly compatible with the latest version of iDRC, and now this contribution enables that confidence. That is a big deal.

But that’s not all. In addition, recall that OpenDFM adds numerous standardized DFM checks to the traditional DRC checks. If you care about DFM, that’s just as big a deal. So now this is a double-win.

Yet there is even more value. If you are a foundry (other than TSMC) or you do business with these other foundries, OpenDFM will enable new efficiency savings for both DRC and DFM at the same time, which was not previously possible. Hmm, that’s a really big deal, too.

But wait, I’m not done yet! Since OpenDFM is being extended by the OpenPDK Coalition to handle brand new efficiency requirements to support ‘targeting’ (defined in a specification offered to Si2 by IBM and the ISDA partners), these targeting extensions to OpenDFM will add even more value to anyone working at leading-edge process nodes. Finally, OpenAccess adopters will find the above OpenDFM features (including those that originated in iDRC) will also help with OpenAccess-based flows. In fact, there are planned OpenAccess enhancements that will also help the users of OpenDFM. So this is really a big win – for everyone in industry.

Over the past week, I have had several email and phone requests regarding a less-than-well-understood topic: IEEE-ISTO. So, I’ll dedicate today’s blog to a PSA (public service announcement) to help others who may be similarly confused and get the main facts straight.

What is IEEE-ISTO? Well, to begin with it is not IEEE. I’d better repeat this main point: IEEE-ISTO is not the same as IEEE. IEEE-ISTO is a separate not-for-profit corporation that is legally separated from the IEEE and has a distinct membership. It’s function is to provide a service for its sponsors, such as legal structure, insurance policies, rudimentary program management, marketing communications, and finance management. The primary value proposition for target industry programs is generally the avoidance of establishing a separate legal entity, which costs in both time and redundant resource expenditures. IEEE-ISTO was formed in 1999, and today has 15 active programs.

It is essential to understand that, while IEEE and IEEE-SA develop true industry standards that must satisfy broadly accepted rules and procedures that protect against discriminatory or exclusive control (nearly identical to the standardization processes used at Si2), this dos not apply to IEEE-ISTO. In fact, IEEE-SA members are not involved with programs of the ISTO and vice-versa (other than by sheer coincidence of a participant working at a company that belongs to both organizations).

The reason why IEEE, IEEE-SA, and Si2 require non-discriminatory, non-exclusive, democratic processes for developing “standards” is the assurance that no single company can hold an entire industry hostage to advantage its own commercial product interests. Of course, a proprietary format / language in popular use may be accepted by the market as a good thing, but everyone understands the terms under which it is being accepted for use (more on what defines an open standard is at: http://chipdesignmag.com/bayer/2010/03/29/what-is-openness). IEEE-ISTO does not impose any of these requirements for their “industry programs”, so it requires a full case-by-case analysis of all details of the specific “program” to determine who has the control and under what terms.

IEEE-ISTO provides a useful service for certain “programs”… let’s just be very clear how ISTO’s “roll-your-own” dot-org service differs from an IEEE standard. Note that Si2 has also provided a very similar service under special request in several instances, including formation of the LEF/DEF TAB (for Cadence) and Liberty TAB (for Synopsys). Si2 policy requires that all public communications make it very clear that these do not qualify as “standards”, they are a special form of collaboration where there is single-company ownership and control, but with advisory input from other selected invitees. If one wishes a term for this category, I’ll suggest using the phrase “de facto standards”.

If you would like more details, you may visit the IEEE-ISTO website, such as this FAQ found at: http://www.ieee-isto.org/faqs .

Of course EDA is a tool industry… or is it? Perhaps our assumptions are out of step with the times – let’s explore this idea further.

We start with the fundamental value proposition of commercial EDA, which is rooted in expertise to improve the efficiency and predictability of designing electronics (I focus on chip design). Of course, expertise in software and algorithms is critical, along with human interface design to support deeply intricate technical decision-making and analysis. So, software is a critical delivery vehicle, no doubt. But is the industry’s value really in the software, or the expertise that created the software? Here is some evidence that points in the other direction.

First, consider the “partner” model of EDA tool development. New software is developed through lots of close interaction with customers, learning the details of their flow, their data, and their methodologies, to incorporate into supporting tools, which are then rolled out in layers of beta sites and evaluations until the customer is willing to use it in a production context. This is arguably a consulting model, highly dependent upon knowledgeable EDA expertise to capture, implement, and adapt to specific and time-varying needs. Very little in EDA is shrink-wrap anymore.

Anyone care to guess the value of EDA software devoid of the development team (such as after an acquisition has gone poorly)? It’s never been just about code.

Next, look at current design technology trends – continually increasing use of commercial IP blocks, created by the vendor and delivered along with domain experts to assist in successful integration. Most of the more complex IP usage is as much “re-do” as “re-use” for at least later portions of the flow – selective alterations to manage die size and power consumption at the front end, and more context-based variations (and DFM concerns) requiring custom re-work in the back-end.

Business trends are also significant. The fabless / foundry model has led to many design houses relying more on their EDA vendors to prove out how the tools work with the foundries. Add to that EDA’s new interest to scope in embedded software (see: http://www.si2.org/?page=1077), which also means more of a service orientation to support domain-specific verification and modeling to complement the tools. Let’s also not forget the new “software as a service” growth area for EDA.

Finally, there’s the financial point of view. Already, almost 30% of EDA revenue comes from IP and services today — not counting the “embedded services” we discussed supporting EDA tool revenue.

I see these trends expanding. EDA serves a very diverse and changing marketplace, with many diverse requirements, and a growing dependency upon customers and foundries to complete the product cycle. Would managing EDA primarily as a service industry better serve it’s future growth? I’d be interested to hear your comments.

Over the last 5 weeks, I have spanned nine countries visiting with Si2’s members across Europe and Asia, returning on Wednesday. Cities included London, Cambridge, Brussels, Eindhoven, Leuven, Paris, Grenoble, Tokyo, Yokohama, Hsinchu, and Seoul. Calling it a “world tour” may be a bit of a stretch, but this is about as close as I’ll ever get (unless my local Austin band suddenly becomes famous and lands a global tour gig, but I’m not holding my breath).

Hectic though they may be, I truly enjoy these annual “tours” – to sit down face-to-face with so many industry leaders in their own work environment, meeting with their engineering teams, and connecting on a much more personal level. These trips offer an opportunity to gain deeper understanding of the needs and priorities of so many companies that are setting the pace for our industry’s growth and innovation. Naturally, there are numerous large corporate heavyweights on our itinerary, but we also visit startups, some working from within “technology incubators” that wow us with amazing levels of innovation, passion, and efficiency. While funding ability within this economic climate varies widely, this creative spirit is alive and well across the globe, just as much as it is within Silicon Valley. By listening to each organization’s unique circumstances, we can then better understand how to architect and phase standards efforts that satisfy the greatest possible set of shared priorities, while avoiding areas of ambiguity or conflict.

While extended economic malaise has left us with permanent tectonic shifts across the industry, I heard loud and clear that standards matter every bit as much today as ever before. In fact, the need to find efficiencies has forced new ways to automate and new ways to collaborate. Most of the time this requires supporting standards as the lifeblood of technical data exchange for enabling effective business commerce. This is true in established areas that need better efficiencies, and even more so for new growth niches that are being held back by confusion and fragmentation.

The topic area that seemed the most timely on this trip was OpenPDK, which took center stage. I should have expected this, because nearly every company touches PDKs in some way, and the data is getting more complex. Achieving commonality is made much more complex because today’s production environments are using a variety of formats and languages that are difficult to replace, yet all know we can and must find ways to do better. There is clearly an increased emphasis on differentiated analog and custom design out there.

OpenAccess is always a primary topic of engagement. I am gratified to hear that many companies are either expanding their use of OpenAccess this year, or planning first production deployment. A large majority are quite pleased with it’s current state; some are glad to hear about recent new features or the in-work enhancements to better scale our operational model. Many have delayed their production deployments for up to several years, to sync with vendor tool upgrade decisions.

I also found that more companies than I had realized have been feeling increased pain in the area of DRC rule decks, and are eagerly awaiting the release of OpenDFM out of the DFM Coalition. The pain levels are primarily associated with managing QA across multiple DRC formats, complications arising from increasing variability and new DFM rules, and complexities due to industrial partnerships requiring sharing of PDKs and libraries.

Low-power is an ever-present priority, but companies are still struggling to fully incorporate low-power intent across their design flows. Part of this is the multi-format issue (this includes some who remain using in-house formats, and are telling their vendors to translate into either CPF or UPF). The general case seems to be starting out with basic low-power intent using UPF for synthesis, then using CPF for the implementation flow. Users of CPF seem very pleased with it and it’s direction. Still, interoperability remains a problem (there was appreciation for the LPC’s recently-released Interoperability Guide that maps between CPF and IEEE-1801).

While many companies care about continued device and feature integration, fewer plan to rely on advanced process nodes to do it. There is good long-term potential for 3D stacked die to fulfill some of that need – but only after a host of technical and business issues can be resolved first. I am not sensing urgency here, but in general solid interest.

In summary, I found that business activity has restored to near-previous levels, with renewed enthusiasm but with fewer staff and a cautious revenue outlook for years to come. The value of standards has not declined, even though the ability to support them with staff resources has become more tightly managed and focused on direct areas of pain and need.

Last month, I wrote a blog describing the “Top Ten Guidelines for Successful Collaboration”, and received some very supportive email responses suggesting that I continue the topic but explore it further. In particular, I was asked to expand on “why collaboration in EDA standards seems to be non-existent”. So, I’d like to discuss the specific challenges that impact the EDA world (this idea from an EDA CEO, mind you), though it really spans our entire design enablement eco-system.

Here is the symptom: EDA has two primary competitors upon which the rest of the eco-system seems to routinely divide, split into two “camps” that cause sustained pain for users, partners, and even EDA’s own eco-system. Examples of this are not hard to find: library formats, design rule formats, high-level HDLs, verification libraries, low-power formats, etc. My email associate cited an ever-present duopoly even where a single standard would seem a clear logical choice. Critics state that this is a sign of an immature industry that fails to grow its market; others note that at least two is far better than five, ten (or none).

So, why does EDA repeat this bad habit, arguably to its own detriment? First of all, the market for EDA tools is in fact highly inelastic, i.e. it is very difficult to create more designers by lowering prices or increasing features, especially in the high-stakes silicon arena. EDA competes in a largely saturated market (with the exception of emerging technology niches). Second, much EDA software has a low barrier to entry by new entrants, or by large EDA customers. This low barrier caps its selling price point, which is the alternative of large customers returning to in-house development (which has higher NRE but lower RE). Third, EDA has developed some “bad habits” in the handling of its business model, often losing what little leverage it has in negotiations just to close a deal in a given quarter. Fourth, EDA has continued to lose clout to more powerful and concentrated market forces – those who actually create the silicon, for example. All of these forces put EDA into a defensive posture, using anything in its arsenal to defend against a transition to a competitor – and that includes formats and standards. This is a natural reaction to these circumstances.

In EDA’s defense, there are times when multiple simultaneous, proprietary approaches are the right business decision, in spite of the lofty goals of collaboration. This can occur when a format becomes tightly linked to a (proprietary) tool algorithm or internal data structure, or when a new tool needs to blaze its own trail with a new (unstable) format.

The real problem for EDA, and for EDA’s customers, is that boundary lines are poorly defined. We hear phrases like “collaborate on standards, compete on tools”, but for EDA formats, languages, and libraries that are at times tightly intertwined with their algorithms (and thus value proposition), this is easier said than done. The fact that everyone in the supply chain may “lose” more shared market opportunity as a result of divergent formats is rarely considered.

I think we can and should do better, but it’s unrealistic to expect EDA to define clear boundaries for itself. Customers must share a large part of the burden here, because for all the talk of common standards, they do not consistently prioritize collaborative results and common standards, for the good of the larger industry, over other immediate needs. The main reason EDA appears worse at collaboration than other industries is due to a perfect storm of reinforcing market forces. The only solution to this is a new, stronger market force – consistent purchasing priorities of EDA’s customer base.