On Oct 20th, the 15th Si2 Conference will take place in Santa Clara, so I’ll use this week’s blog to explain and summarize what I think is most significant about it.

Many of you may traditionally know this event as the “OpenAccess Conference” – so why did we change the name? To be certain, this event retains a major emphasis on OpenAccess advancements as in years past. However, since Si2 now has more active projects, we will also cover engineering advancements and adoption progress among all the increasingly inter-related areas of OpenAccess, Design for Manufacturability (DFM), Low Power design and the newest Coalition for Open PDKs. To accommodate the growing amount of material while still holding to a single-day event, we are using parallel tracks.

There will be a DFM session which will cover the first ever meta language standard, OpenDFM, to describe DRC and DFM checks in a tool-agnostic fashion. The session will also include a presentation on the concepts driving process targeting which is becoming a key enabler for technology nodes at 32nm and below. Yet another session will cover the exciting new activity in the industry on truly open Process Design Kits. This Coalition has taken off very rapidly due
to the pent up demand in the industry for standards at this fundamental level of design. In addition, OpenAccess is growing dramatically and is now essentially a must have for all industry players and the talks in this area will vouch for that. A session on Low Power will discuss recent Low Power Coalition work in power modeling standards, an update on the upcoming CPF 2.0 standard which will include interoperability with other power-aware formats, and an example by Renesas Electronics Corp. of a power-aware design flow using some of these techniques.

I’m personally excited about the introduction of multi-threading into OpenAccess and rapid progress for a common (standard) scripting language architecture and scripting language interfaces for all major languages. These are major advancements to OpenAccess in both performance and flexibility – many designers work with scripts extensively in their design flows during chip development. I’m also very excited about OpenDFM, which promises to dramatically improve DRC deck development / runtime efficiencies (from 5x to 20x) while enabling improved portability and choice among foundries and tools and standardizing DFM checks to maximize effective yield.

In power-aware design, I like the quality technical work toward new power modeling standards, as well as major new features upcoming with CPF v2.0. ARM and Renesas will be explaining their power-intent based design flows using CPF. Finally, the new OpenPDK Coalition will present progress and plans for enhanced symbol / schematic support, and the new “eDRM” standard that will specify interoperable PDK intent once, and then use plug-ins to generate file sets supporting the various PDK flows used by foundries.

Finally, as in prior conferences, there will be an evening session that will showcase demos of advances based on the technologies offered by Si2. This session will also serve as a valuable opportunity for networking. Refreshments will be served.

The detailed agenda is located at this link: http://www.si2.org/?page=1262