In my last blog, I introduced six common themes relevant to 5-year design standard needs that emerge from reviewing the ITRS Roadmap. This week, let’s begin exploring each of these six areas in greater depth.

I) 3D IC / TSV Design Support: Unless you’ve been hiding under a rock, you’ve probably noticed lots of industry investment and discussion surrounding 3D stacked die, particularly using through-silicon-vias (TSVs), and it’s not hard to understand why. The promise of up to 40% reduction in cost and energy consumption, 10x increased memory bandwidth, shorter interconnects for faster critical path performance, and reduced development risk are all attractive. However the design-side challenges span both system and silicon complexities simultaneously, requiring sufficient ability to analyze electrical, physical, thermal, and mechanical trade-offs for a balanced best-fit result. While most current EDA capability can extend reasonably well to support 3D, certain added information must be shared across tools to enable necessary choke points. Standardization is not merely an issue among EDA tool vendors for these data objects, it also affects whether design houses can “mix and stack” logic die from one provider with memory die from multiple providers and designs targeting more than one process / foundry. To enable these needs, industry standards will need to support certain types of data exchange between timing, power, thermal, stress, physical, packaging, and 3D floorplanning tools (a.k.a. pathfinding), all architected to work for reusable IP blocks. The standards support must span processor, memory, SoC, analog, and RF fabrics as well. In addition, PDK standards support will be needed that comprehend 3D-specific process parameters. Industry can expect that, over time, this may include 3D extensions to existing OpenAccess, OpenPDK, and OpenDFM standards.

II) Variation-Aware Everything: The ITRS brings into focus the reality that managing variations is all about managing risk. We can no longer ignore the fact that designing without a good understanding and awareness of variations and their impact is essential to delivering working products on time and budget, particularly at sub-40nm process nodes. Today’s leading-process chips pack more transistors and wires, more sub-wavelength patterns, more mask layers, and more DFM manufacturing variations. 3D will only add additional variation due to wafer thinning, alignment issues, thermal variation, and so on. These unpredictable physics couplings and device parameter deviations roll up to affect nearly every electrical parameter at the design level. Since trying to manage variation in values adds more numbers to pass and more perturbations to compute, statistical methods will grow in use – and not just for digital timing – variation-aware modeling will emerge as a central issue in advanced design flows. Some of the Si2 standards areas where increased variation support will likely be needed include extensions to OpenDFM, a “DFM library” with an open API, power modeling support for variations, and additional OpenAccess data objects to enable variation management, including design constraints.

III) IP Block Modeling And Integration: While reusing IP design content is hardly new, the challenges are increasing even as the ITRS predicts a continued increase in dependence upon reusable IP. Quality issues are getting harder to manage at smaller process geometries (due to more variations), support that spans multiple foundries is becoming trickier and more costly. Power intent must be “golden” to support consistent reuse and quality measures, and necessary to support a maintainable “mix and match” deployment model. Larger, more complex IP blocks (such as processor cores) require more complex models — and across multiple abstraction levels. Thus it is no surprise that the challenges of integrating and verifying IP blocks is resulting in more and more tape-out delays and re-spins.

With emerging ITRS technology issues making the job of IP modeling and integration increasingly difficult, what must standards do to improve this situation? While IP reuse standardization is a fundamentally complex topic (look for an upcoming article in Chip Design where I cover more detail), in summary there are efficiency gains our industry could pursue at the process / foundry layer, the electrical / signal interface layer, and the block verification layer. At all layers we could improve interoperability in how we specify and verify power consumption when mixing IP blocks, and similarly for physical verification. Some in industry are beginning to suggest that OpenAccess may, in the future, serve as a better delivery vehicle for consistent distribution and integration of IP block content. I thus see potential enhancements to OpenAccess, OpenDFM, and CPF as some opportunities to add value to address the needs above.

As we begin to look at addressing a wide range of standardization challenges ahead, I believe it is important for industry leaders to better communicate on the standards implications of the ITRS challenges themselves, to align on the time-sequenced specific needs first. This would go a long ways to help organize a more orderly focus of industry resources toward solving these issues efficiently.

The three remaining 5-year standardization themes will be addressed in my next blog. As always, your inputs are appreciated!