Recently there has been some media attention around one politician’s claim that the President’s speech writers hijacked his catch phrase about “doing really big things”. Well, I’m willing to bet that neither of them had EDA or chip design flows in mind when talking about doing “big things”. That’s too bad, since I think we could use a bit of lively discussion about the challenges and opportunities ahead – and how our industry should drive forward with real vision. Perhaps its the engineer side of us that balks at the idea we should get too excited about anything, as though it’s all dull incremental add-ons to existing technology. Even I have frequently stated publicly that “revolutions always happen through evolutionary means”, which is to underscore that standards don’t just suddenly replace their predecessors. Rather, adoption must consider co-existence and migration paths instead to be successful.

Yet there are some areas where I get excited about the possibilities. OpenAccess was one of those “vision things” years ago for me, and now it is paying increasingly large dividends across the supply chain. I think low power is another one of those exciting areas for improving design flows, ripe with opportunity to dramatically change our ability to design in silicon in the coming years. As I look at the progress we’ve made so far, and where we need to go to stay on track with the ITRS roadmap, we have only just begun, with far more improvement necessary to avoid stalling out in how much we can design in silicon.

Here’s why I am excited about the possibilities to help drive positive industry change in the area of power. First, the need is huge – ITRS integration trends trends vastly out-pace our trajectory of low-power improvements made in recent years. Second, nearly every vertical market segment in semiconductors and systems has made power a first-order concern and priority in design. Third, power is inherently more nuanced and multi-dimensional – switching vs. leakage, peak vs. average, battery-life vs. thermal, etc. Fourth, power design interdependencies extend from silicon to software stacks, into package and board, affect emerging trends like 3D stacked die, and so on.

Yet there are huge challenges that must be overcome to step up our rate of progress to meet the coming needs. Some challenges will be addressed through methodology, others with new or enhanced tools, and some will require new and enhanced industry standards for collaboration to work efficiently. Methodology was once seen as an area well outside the scope of standardization, however these days some alignment in methodology is recognized as a valuable complement to other more differentiated methodologies, as just witnessed in the verification arena with the successful approval of UVM.

There are three needs in the area of power-related standards: a) description of power intent; b) modeling of power information required by tools across the flow; and c) interfaces to efficiently pass power data between tools, databases, and formats. Note that power intent describes top-down designer decisions and constraints, while modeling describes bottoms-up abstractions of the physics. The intersection of top-down intent with bottoms-up physics then occurs through EDA tools across the flow, which in all cases will be a multi-vendor flow and thus these standards are both essential.

Incidentally, the Low Power Coalition (LPC) just last week released Common Power Format v2.0 (CPF), with over 100 pages of enhanced features and capability to be used by designers (for details, see http://www.si2.org/?page=1325). The LPC is also expanding their freely-available Interoperability Guide for those companies working with UPF to include these new CPF v2.0 features, which includes CPF commands designed to enable greater compatibility with UPF. Not long ago, the LPC also released the “High-Level Power Modeling Requirements” document, which describes the motivations and requirements for accurately and efficiently describing the power behavior of arbitrarily complex functions (http://www.si2.org/?page=1239)

I believe the semiconductor and EDA industries need to come together to recognize the challenges and exciting opportunities ahead for power-aware design flows, and invest more in proactively solving these challenges which could otherwise threaten to limit future design growth. While many areas are needed and will be worked in the proprietary realm, we already know that aligning on standards will be required to hit economic “critical mass” when we want to raise to higher levels of design abstraction. Working together, I am confident that we can help enable faster and further progress in doing “really big things” for low-power design.