Collaborative Advantage

In February, the Low Power Coalition (LPC) published their third release of the Common Power Format standard, with over 100 pages of (backward-compatible) enhanced capabilities including added CPF commands to enable greater compatibility with IEEE 1801. The LPC also created the CPF/UPF Interoperability Guide to relate commands in CPF and equivalent mapping to 1801-2009. Yet there are limitations to what can be mapped, notably with the older UPF 1.0 constructs.

Many industry-leading companies spanning fabless, IDM, IP, OEM, and EDA have underscored to Si2 the ongoing negative impact on productivity when trying to work with both CPF and UPF/1801-2009 in tool flows, despite best-effort command mapping. The root of the problem is deeper than syntax differences – it is about incompatible methodologies for how to organize and manage low power intent data. This became clear after recent customer visits in the U.S., Asia, and Europe, so Si2 chose to offer our help and leadership in resolving those gaps with a coordinated effort being called “OpenLPM” (LPM = Low Power Methodology).

OpenLPM is not a new standard or new project — it is a proactive approach by Si2 and our LPC members to resolve these productivity challenges by contributing certain CPF technology to the P1801 Working Group (WG). This allows the P1801 WG to enhance the capabilities and use cases (methodologies) in the 1801 specification for a smoother overall flow when working with both environments. Three primary features are required for a converged low-power methodology:
(a) Power-domain-centric organization of intent;
(b) Successive refinement of power intent detail; and
(c) Formal support of hierarchy for IP reuse.

Last week, Si2 and the LPC made a technology contribution of these features from CPF to the P1801 WG. It is Si2’s sincere hope that these will not only be helpful to improve the next revision of 1801 (targeted for 2012), but will also make major inroads in reducing the friction in working with multi-vendor tool flows. The next step will be for the P1801 WG to determine which portions of the Si2 contribution (if any) to accept for incorporation into the next revision of 1801. Si2 has been an active member of the P1801 WG and will continue to support the LPC charter to lead in low-power flows, independent of format.

A press release explaining additional details of OpenLPM and including quotes of support from many industry leaders can be found at: http://www.si2.org/?page=1348

The Design Automation Conference (DAC) is an annual ritual in the world of EDA and the electronics industry, and it remains the single largest venue for announcing progress in Si2 standards, sharing that progress in (free) technical workshops, demonstrating that progress in demos, and celebrating our collaborative successes together (as in face-to-face, an increasingly rare opportunity in this Internet age). In this blog I’ll quickly summarize “everything DAC” from an Si2 perspective. With nearly 100 corporate members, there’s a lot going on.

OpenDFM and OpenPDK Team Up: While the DFM and OpenPDK coalitions have definitely unique goals, scope, and membership, there are clearly areas where each set of standards can help the other set. Monday morning’s DAC Workshop is titled “Synergies in IC Design: PDK and DFM Standards Working Together” for good reason. This is a great opportunity to learn more about two very exciting areas at the same time. OpenDFM rules bridge the gap between a layout style that allows only a few, very restricted layout patterns and a style that allows purely arbitrary layouts. Second, there is ongoing effort to standardize a common format for representing parasitic information and to better handle manufacturing variability. This has implications in how this data is represented in PDKs and how they affect the modeling of design parameters for power, timing, and SI analysis. More detailed information is here: http://www.dac.com/workshops+_+colocated+events.aspx?event=47&topic=3

OpenAccess For Everyone! “It’s not just for programmers anymore”… The OpenAccess Scripting Language Workshop shows off this new framework infrastructure (based on SWIG) that enables a wide variety of popular scripting languages. Learn all about how to connect with OpenAccess using Tcl, Perl, Python, or Ruby, either integrated with native C++ code or as stand-alone programs. Engineers use scripting languages as part of their daily work. This tutorial will provide an invaluable knowledge base of what is available through programming examples created by Si2 as a complement to the popular C++ API tutorial. And very importantly..since we would have no speakers or attendees during the middle of the session, we have a built-in break so everyone can go see the “Woz”, Steve Wozinak’s, Keynote Address. For more information, see: http://www.dac.com/workshops+_+colocated+events.aspx?event=1&topic=8

You can return to the session, without missing anything, then stay in the same room for…..

Party With A Purpose: In celebration of over 23 years of service to the IC design industry, refreshments and light hors d’oeuvres will be served at the Annual Si2 Open Reception Monday afternoon. This reception is free and open to all who are interested in Si2 activities such as OpenAccess, DFM, low-power design, 3D ICs, and OpenPDKs. The keynote speaker will be Philippe Magarshack, Group Vice-President – Central R&D, STMicroelectronics. The title of his talk will be “The Value of Open Standards for Systems-on-Chips in 28nm and Below”. As always, I will also present a short summary of Si2, our exciting year’s accomplishments, and new directions ahead. This party will end in time for everyone to attend the nightly DAC Reception at 6PM.
For more information, see: http://www.dac.com/additional+meetings.aspx?event=64&topic=13

Three-Ring Circus at the Si2 Booth (#1631): It’s a busy place at this year’s Si2 booth, with 7 Si2 Members demonstrations of products that integrate Si2 standards and collaborative technology, including Analog Rails, IBM, Cadence, Magma, Mentor Graphics, Pulsic, and Synopsys. These companies will be showing how Si2 standards developed by the OpenAccess Coalition, the OpenPDK Coalition, the Low Power Coalition, the Open Modeling TAB and the Design for Manufacturability Coalition can provide innovative approaches to critical IC design flow issues.

The EDA industry has played a pivotal role in the semiconductor supply chain since it’s origins in the early eighties. Yet, nearly 30 years later, we have an important issue to work through as an industry. What’s at stake is nothing less than EDA’s fundamental role in supporting an evolving semiconductor industry over the next decade, not to mention what kind of standards will be required to support this ecosystem. Because “EDA360″ is now in our current vernacular, and so closely connected with these trends, I’ll address it as part of my industry analysis.

There is no need to repeat the unavoidable trends of the electronics industry and semiconductor’s role within it. The primary, sustainable value in electronics continues to migrate upstream above the silicon itself – it’s about the system, the application, the content, and the inter-connected infrastructure that delivers that content. In this era, the silicon that wins in the market will be the silicon that gets the most out of the software applications and neighboring hardware to realize that value potential. EDA’s role should be to enable that optimization of silicon within the context of the full product. Let’s dissect what that really means and why we’re not there yet.

Optimizing the myriad trade-offs of silicon features, performance, power, area, and cost are hard enough. However, when much of the feature set resides in the software stack (some of which is being designed in parallel), that job becomes much harder. It gets more difficult when other software components and other silicon components comes from other companies. And it becomes near impossible if the critical information needed to make signoff level analyses, estimates, and judgment calls is unavailable. In this context, more and more of the engineering team’s time is being focused outside of traditional EDA scope, because decisions about the system can only be made outside of EDA. This is not good for EDA’s perceived value-added role in building systems on a chip.

I am not making a case for getting EDA into the crowded, low-margin software development world, in fact quite the opposite. Rather, EDA’s deep silicon expertise uniquely qualifies it to take the lead in mapping what essential information from the software world must be passed into the “function / timing / power / noise / DFM” world, then using that to perform new and wonderful algorithms that guide the decision space for an optimal end product experience. EDA should want that focus and value happening within it’s tool flow, where it belongs. Bringing that value more visibly into EDA’s arena is the best way to deliver long-term growth.

If one were to ask the major EDA vendors “what is EDA360?”, there would clearly be a diversity of responses. Cadence, having issued a white paper describing the vision in pretty good depth, has defined a fairly clear answer to this question. I have also read articles from several other EDA executives and leading niche vendors, expounding the EDA360 concept and the need for a new EDA vision. A handful of other articles / blogs have focused on various aspects of EDA360, generally quite positive on the idea… but with a healthy dose of skepticism about either the motives of Cadence or the ability of this EDA industry to adapt. Other major EDA vendors appear to have kept a low profile, perhaps hoping it will just fade away.

Regardless of the company that coined “EDA360″, are the principles well aligned with the trends described above? If so, then what do we choose to do as a response? Some might argue that any proposal offered by a single EDA vendor would be met with identical skepticism by that vendor’s competition and thus cannot succeed. If that is true, then how does the EDA industry ever coordinate on a direction for it’s own future? Or, are we just making the conscious decision not to coordinate? There is little doubt in my mind that the system-view “value shift” is happening, and EDA will either be at the center of where these critical, intersecting trade-offs occur, or run the risk of being left off to the side.

I see an increasingly interconnected world, where economic business models are forcing greater collaboration and coordination to deal with intricate complexities. I see a vision of well-timed standards playing an increasing role to open up new market opportunities, allowing the industry to hit “economic critical mass” by lowering cost and improving efficiency.

So, if not “EDA360″, then what? What is our strategic alternate path to grow our collective vision? Can EDA change itself, or will it forever remain confined to the minor role it originally filled in the 80’s and early 90’s? Regardless of the label used, I believe the EDA industry is up to the task and wants to embrace a new major role in “next chapter” of growth. I’d like to hear your thoughts on how we get there.

It has been awhile since my last blog, as I have been “touring” across numerous countries in Asia, Europe, and the U.S. This annual “tour” of countries, however, is an essential part of building up relationships, as well as listening to the industry at large. In this blog, I’ll share a few common themes that emerged from this extensive travel period.

One of my favorite quotes from author Steven Covey is “Seek first to understand, then to be understood”. It should apply universally, but especially in marketing (where young marketeers mistake their function as merely being to “push” products). Seeking to understand the range of needs and priorities across an industry takes many forms, but nothing replaces quality face to face time with both executive management as well as the technologists. For effective collaboration, it is critical to listen to the needs as they evolve, internalize the messages, then optimize the engineering solution so that the result will get adopted and be effective. Because Si2 has a wide range of project areas, differing teams may care about different areas for their company.

Some themes are common every year, but others are more specific to our times. For example, we have continually seen OpenAccess adoption build and extend in scope, little by little. However, this year we are seeing much more direct engagement by foundries of all types, and usage scenarios well beyond traditional custom CMOS design (more digital, more PCB / package, 3D, and even photonics waveguides!). There is tremendous recent interest in using the new OA scripting language interfaces, which extends the use model for OA from just C++ developers to more project-level engineers.

In low power, the theme of interoperability has been a constant pain point over the past five years. What we heard new is not simply about mapping across two standard formats, but much more depth relating to issues in how the power intent information must be organized and managed differently across multi-vendor flows. Si2 and the Low Power Coalition are preparing an answer to lead a broad converged solution to this growing problem, so stay tuned. The other new theme is rapidly growing level of interest in defining standards for power modeling (which LPC members have been actively working on already).

There has been much talk around 3D stacked die in recent years, and this past year more focus on design standards for 2.5D and 3D silicon. Yet I am now hearing a strong – almost urgent – theme around getting started on certain standards to support production 3D chip delivery by 2013-2014. That means (multi-vendor) design flows must be ready the prior year, and that those standards must be ready a year before that (yes, that means by early 2012, which will be quite a trick).

There were many other interesting details and reinforcements, but these are several new themes that repeatedly came up during these trips. If you have other perspectives to share on these or additional themes, I’d be interested to hear about them.

Recently there has been some media attention around one politician’s claim that the President’s speech writers hijacked his catch phrase about “doing really big things”. Well, I’m willing to bet that neither of them had EDA or chip design flows in mind when talking about doing “big things”. That’s too bad, since I think we could use a bit of lively discussion about the challenges and opportunities ahead – and how our industry should drive forward with real vision. Perhaps its the engineer side of us that balks at the idea we should get too excited about anything, as though it’s all dull incremental add-ons to existing technology. Even I have frequently stated publicly that “revolutions always happen through evolutionary means”, which is to underscore that standards don’t just suddenly replace their predecessors. Rather, adoption must consider co-existence and migration paths instead to be successful.

Yet there are some areas where I get excited about the possibilities. OpenAccess was one of those “vision things” years ago for me, and now it is paying increasingly large dividends across the supply chain. I think low power is another one of those exciting areas for improving design flows, ripe with opportunity to dramatically change our ability to design in silicon in the coming years. As I look at the progress we’ve made so far, and where we need to go to stay on track with the ITRS roadmap, we have only just begun, with far more improvement necessary to avoid stalling out in how much we can design in silicon.

Here’s why I am excited about the possibilities to help drive positive industry change in the area of power. First, the need is huge – ITRS integration trends trends vastly out-pace our trajectory of low-power improvements made in recent years. Second, nearly every vertical market segment in semiconductors and systems has made power a first-order concern and priority in design. Third, power is inherently more nuanced and multi-dimensional – switching vs. leakage, peak vs. average, battery-life vs. thermal, etc. Fourth, power design interdependencies extend from silicon to software stacks, into package and board, affect emerging trends like 3D stacked die, and so on.

Yet there are huge challenges that must be overcome to step up our rate of progress to meet the coming needs. Some challenges will be addressed through methodology, others with new or enhanced tools, and some will require new and enhanced industry standards for collaboration to work efficiently. Methodology was once seen as an area well outside the scope of standardization, however these days some alignment in methodology is recognized as a valuable complement to other more differentiated methodologies, as just witnessed in the verification arena with the successful approval of UVM.

There are three needs in the area of power-related standards: a) description of power intent; b) modeling of power information required by tools across the flow; and c) interfaces to efficiently pass power data between tools, databases, and formats. Note that power intent describes top-down designer decisions and constraints, while modeling describes bottoms-up abstractions of the physics. The intersection of top-down intent with bottoms-up physics then occurs through EDA tools across the flow, which in all cases will be a multi-vendor flow and thus these standards are both essential.

Incidentally, the Low Power Coalition (LPC) just last week released Common Power Format v2.0 (CPF), with over 100 pages of enhanced features and capability to be used by designers (for details, see http://www.si2.org/?page=1325). The LPC is also expanding their freely-available Interoperability Guide for those companies working with UPF to include these new CPF v2.0 features, which includes CPF commands designed to enable greater compatibility with UPF. Not long ago, the LPC also released the “High-Level Power Modeling Requirements” document, which describes the motivations and requirements for accurately and efficiently describing the power behavior of arbitrarily complex functions (http://www.si2.org/?page=1239)

I believe the semiconductor and EDA industries need to come together to recognize the challenges and exciting opportunities ahead for power-aware design flows, and invest more in proactively solving these challenges which could otherwise threaten to limit future design growth. While many areas are needed and will be worked in the proprietary realm, we already know that aligning on standards will be required to hit economic “critical mass” when we want to raise to higher levels of design abstraction. Working together, I am confident that we can help enable faster and further progress in doing “really big things” for low-power design.

When I came over to Si2 after 20+ years in the semiconductor industry, I was critical of how many standard specifications were created and approved, but then poorly adopted. My main point was, and remains, that there is no commercial value to a standard until widely adopted, so the industry needed process improvement applied to how we go about ensuring our investments are not wasted. Part of that process is clarity and alignment of need for a proposed standard – who needs it, and when it must be ready. Too early and it has no market; too late, and the concrete of “incompatibility chaos” has set and dried. Another aspect is supporting the life cycle needs of a standard through adoption – what is required to remove barriers that prevent rapid and consistent adoption across industry?

Creation of a specification is one thing, but adoption is another, often more difficult, challenge. Adoption aids for a standard may include education, training, test cases, labs, parsers, header files, or even a full “reference implementation” or “reference flow”. Sometimes, supporting software may provide useful bindings to popular scripting languages, enable translation among other formats and APIs, and might include value-added utilities to aid integration testing, debugging, and data inspection / analysis. Website support for adoption should consider offering on-line discussion forums, bug trackers, and new feature requests. In addition, new contributions of technical requirements, data models, or code implementations may require appropriate licenses, “certificates of authenticity”, and legal protections for all other participating members. Finally, effective standards development needs to work acceptably well in a global context – which may mean multiple languages and widely-varying time zones.

Not all standards require such heavy lifting. For example, Si2’s ECSM Noise standard is a mere 31 pages, describing straightforward file format syntax. By contrast, OpenAccess includes nearly 700 C++ classes, dozens of information model diagrams, plus over 1100 pages that define the API standard. This standard is supported by over 1.5 million lines of code, updated multiple times each year (along with training, labs, etc). OpenAccess could not have succeeded without this strong and consistent support.

Most standards will fall somewhere in between those extremes. The key point: plan for adoption as part of the development of the standard to avoid wasting resources. This does not mean that success of a standard is assured – many external variables come into play, just as with any product introduced into a market. One of the ways to improve the odds is through a large and broad set of active stakeholders working together on the open standard, with equal rights and equal opportunities.

At Si2, another way we help the odds is by defining specific adoption success metrics each year, for accountability to results and incentive to find ways around adoption barriers. These metrics are approved by Si2’s Board of Directors, as are the end-of-year ratings. I would like to encourage all standards development bodies to similarly define adoption metrics — and be held accountable for achieving them.

In a subsequent blog, I will explain more about how certain kinds of supporting adoption aids can open up new standardization possibilities in creating compatibility, even when the concrete has set on any number of competing existing formats. Stay tuned.

This is the final installment of my three-part series that has been exploring the potential impact on design standards from common themes found in the International Technology Roadmap For Semiconductors (ITRS). For quick review, the six themes are:

* 3D IC / TSV Design Support
* Variation-Aware Everything
* IP Block Modeling and Integration
* Power-Aware System / Architecture Optimization
* More Analog / RF Automation
* Value Shift to Software Integration

We’ve already discussed the first three in the last blog, so now let’s discuss themes 4-6.

IV) Power-Aware System / Architecture Optimization: The ITRS estimates that, over the next 5 years, the emphasis on minimizing power in designing chips will shift dramatically from the physical level (at roughly 50% in 2009) to the ESL architectural level (30%) and ESL behavioral level (50%). This makes intuitive sense, in that the design of silicon is increasingly throttled by battery life (for mobility products) or thermal limits (for servers). Furthermore, I argue that designing for power optimization is a fundamentally more complex task than timing optimization, for several reasons. First, it spans all fabrics – digital, analog, and RF – and requires managing both active and leakage currents. Second, sometimes knowing peak power is more important, at other times average power takes priority. Third, local power / thermal / EM problems force sensitivity to physical locality (in 2D, or possibly 3D). Fourth, although power and ground nets are “invisible” in the RTL / behavioral code, these nets become “functional” in terms of affecting power states. Finally, much of the switching activity of the transistors is being determined by embedded software.

The EDA industry is not yet prepared for these challenges – and standards will be an important link in enabling critical mass adoption. Standardization is needed in modeling power at multiple abstraction levels, particularly ESL and also RTL levels. These will, in turn, allow the community to develop models needed for the EDA applications to do their job. Another need will be a communication “bridge” between the hardware-centric design flow and the software development flow, so that certain parameters, constraints, and abstractions can be passed from one in-work context to the other. We also see value in OpenAccess API extensions that will ease the ability for “what if” power trade-offs between a wide variety of tools. Early work on this has already started within the Low Power Coalition, being dubbed “OpenPower”. Finally, we know that chip designers still suffer from a lack of power intent format interoperability in today’s flows. CPF has just been enhanced with this in mind, and in time we should expect the same with UPF as well.

V) More Analog / RF Automation: The ITRS categorizes the emergence of analog / RF, HV power, passives, sensors / actuators, and biochips as “More Than Moore” – a major trend as non-digital content increasingly interacts with a digitized world. We already see this, with a growing number of radios in every smartphone, sensors for camera, video, audio, etc. The OpenAccess standard has enjoyed strong market growth in part because of its foundational role in the analog / custom space, and rapidly growing foundry support for analog / RF. Yet EDA provides relatively little support for analog automation as compared to its digital counterpart, even though the ITRS predicts much more integration of non-digital content. Analog / RF standardization priorities include extensions to OpenDFM to improve yield and design centering, extensions to CPF for explicit analog / RF / MEMS support, and of course a broad and capable standardized solution for Process Design Kits (OpenPDK) addressing analog / RF / MEMS needs.

VI) Value Shift to Software Integration: The value of silicon was once self-contained: the SoC performed a set of specified functions at a certain cost per die, and a disk controller… well, controlled a disk! In the future, less of the differentiating value in a particular silicon design will be rooted in what it can do by itself, but rather by the quality of integration with the O.S. software / application stack sitting above it. It will be very hard to compete on functionality, performance, power, or cost without an innate understanding of the overall product’s priorities and the software that implements those priorities. In general, today’s EDA design flows are woefully ill-equipped for those trade-offs. How can we, as an industry, expand — even redefine — our “field of view” such that new tools and new interfaces work with a broader co-development perspective? How do we, as an industry, align our views? How can we set a common template for automating this new methodology? Standards are a primary means of aligning how an industry communicates data with each other.

In truth, we are not yet ready to define standards to address those questions. Honestly, we barely understand the questions at this stage, let alone the solutions, to speak nothing of implementing a desired solution in a standard. However, it is essential that we begin the dialog, and force ourselves not to delay incremental progress towards these goals. Whether the semiconductor and EDA communities are ready or not, the marketplace will transition to a more holistic interpretation of value from silicon… and we must be able to make design trade-offs against a much larger set of data that impacts the end products. Standards will help us adapt without creating a Tower of Babel of incoherent and incompatible interfaces.

While we cannot yet know what standards will be needed here, we can expect the answer to be a blend of expanding many existing, proven standards, plus the addition of several targeted new standards (hopefully timed properly to meet market readiness). In this way, we can all work together through “co-opetition” to expand the way we deliver semiconductor value to an expanding product world.

In my last blog, I introduced six common themes relevant to 5-year design standard needs that emerge from reviewing the ITRS Roadmap. This week, let’s begin exploring each of these six areas in greater depth.

I) 3D IC / TSV Design Support: Unless you’ve been hiding under a rock, you’ve probably noticed lots of industry investment and discussion surrounding 3D stacked die, particularly using through-silicon-vias (TSVs), and it’s not hard to understand why. The promise of up to 40% reduction in cost and energy consumption, 10x increased memory bandwidth, shorter interconnects for faster critical path performance, and reduced development risk are all attractive. However the design-side challenges span both system and silicon complexities simultaneously, requiring sufficient ability to analyze electrical, physical, thermal, and mechanical trade-offs for a balanced best-fit result. While most current EDA capability can extend reasonably well to support 3D, certain added information must be shared across tools to enable necessary choke points. Standardization is not merely an issue among EDA tool vendors for these data objects, it also affects whether design houses can “mix and stack” logic die from one provider with memory die from multiple providers and designs targeting more than one process / foundry. To enable these needs, industry standards will need to support certain types of data exchange between timing, power, thermal, stress, physical, packaging, and 3D floorplanning tools (a.k.a. pathfinding), all architected to work for reusable IP blocks. The standards support must span processor, memory, SoC, analog, and RF fabrics as well. In addition, PDK standards support will be needed that comprehend 3D-specific process parameters. Industry can expect that, over time, this may include 3D extensions to existing OpenAccess, OpenPDK, and OpenDFM standards.

II) Variation-Aware Everything: The ITRS brings into focus the reality that managing variations is all about managing risk. We can no longer ignore the fact that designing without a good understanding and awareness of variations and their impact is essential to delivering working products on time and budget, particularly at sub-40nm process nodes. Today’s leading-process chips pack more transistors and wires, more sub-wavelength patterns, more mask layers, and more DFM manufacturing variations. 3D will only add additional variation due to wafer thinning, alignment issues, thermal variation, and so on. These unpredictable physics couplings and device parameter deviations roll up to affect nearly every electrical parameter at the design level. Since trying to manage variation in values adds more numbers to pass and more perturbations to compute, statistical methods will grow in use – and not just for digital timing – variation-aware modeling will emerge as a central issue in advanced design flows. Some of the Si2 standards areas where increased variation support will likely be needed include extensions to OpenDFM, a “DFM library” with an open API, power modeling support for variations, and additional OpenAccess data objects to enable variation management, including design constraints.

III) IP Block Modeling And Integration: While reusing IP design content is hardly new, the challenges are increasing even as the ITRS predicts a continued increase in dependence upon reusable IP. Quality issues are getting harder to manage at smaller process geometries (due to more variations), support that spans multiple foundries is becoming trickier and more costly. Power intent must be “golden” to support consistent reuse and quality measures, and necessary to support a maintainable “mix and match” deployment model. Larger, more complex IP blocks (such as processor cores) require more complex models — and across multiple abstraction levels. Thus it is no surprise that the challenges of integrating and verifying IP blocks is resulting in more and more tape-out delays and re-spins.

With emerging ITRS technology issues making the job of IP modeling and integration increasingly difficult, what must standards do to improve this situation? While IP reuse standardization is a fundamentally complex topic (look for an upcoming article in Chip Design where I cover more detail), in summary there are efficiency gains our industry could pursue at the process / foundry layer, the electrical / signal interface layer, and the block verification layer. At all layers we could improve interoperability in how we specify and verify power consumption when mixing IP blocks, and similarly for physical verification. Some in industry are beginning to suggest that OpenAccess may, in the future, serve as a better delivery vehicle for consistent distribution and integration of IP block content. I thus see potential enhancements to OpenAccess, OpenDFM, and CPF as some opportunities to add value to address the needs above.

As we begin to look at addressing a wide range of standardization challenges ahead, I believe it is important for industry leaders to better communicate on the standards implications of the ITRS challenges themselves, to align on the time-sequenced specific needs first. This would go a long ways to help organize a more orderly focus of industry resources toward solving these issues efficiently.

The three remaining 5-year standardization themes will be addressed in my next blog. As always, your inputs are appreciated!

It is to our mutual benefit to continue making advancements that further our capability and efficiency in designing chips and electronic systems, especially during difficult economic times (where we simply cannot afford to work inefficiently). In this regard, the International Technology Roadmap for Semiconductors (ITRS) remains a useful foundation for aligning our industry toward near-term and long-term challenges and potential solutions. In this blog, the first of a multi-part series, I will begin with a summary of 6 key emerging design trends culled from the ITRS, with an eye toward how we can embrace and help further commercial adoption of these directions through a focus of attention on enabling standards technology. If we care about accelerating our improvements, then we need to care about how to knock down all barriers along their path.

Let’s begin with the recognition that continuing this pace of innovation requires simultaneous advances, stretching us in opposite directions. “Silicon Complexity” represents the problems of the small – more details, more of them, and more accuracy. “System Complexity” addresses the problems of the large – more abstract and diverse content, less well understood, but essential to utilize all that raw silicon potential. In addition to technology challenges, changing business models are equally dramatic. The success of the “fabless / fab-lite / foundry” business model has created more M:N data exchanges across company borders, created a shift in power, and made more designs possible. Also, emerging markets not only increased unit volumes, but also added severe margin pressure, which in turn adds pressure on increased efficiencies in design flows.

The ITRS explains how we will grow beyond CMOS scaling – including “More Moore” scaling (but not confined to CMOS transistors), plus “More Than Moore” functional diversification, as well as higher value silicon-based sub-systems that reach closer to the end-user. All of these forces are the foundation for large-scale change ahead. I see 6 recurring themes represented in the ITRS and around industry discussions that will have a large impact on design flows:
• 3D IC / TSV Design Support
• Variation-Aware Everything
• IP Block Modeling and Integration
• Power-Aware System / Architecture Optimization
• More Analog / RF Automation
• Value Shift to Software Integration
So, those are the key areas to watch – but just watching and waiting won’t be enough. In the coming weeks, I will expand on each of these six areas, explaining the motivations, challenges, and focus areas where extensions to existing (and some new) standards can help unblock adoption barriers so that our own industry can be most effective for years to come.

Today, Si2 announced the first official release of the OpenDFM standard — an open, high-level DRC meta-language that generates popular verification formats to support multiple DRC engines with no loss of accuracy or performance. OpenDFM utilizes a more compact notation for physical verification than traditional DRC rules, and incorporates advanced DFM checks defined by the DFM Coalition. This is a major announcement that demonstrates the real power of “innovation through collaboration” – where industry thought leaders across the supply chain have worked alongside Si2 staff to create and test a new standard that saves substantial time and money while increasing efficiency and portability. For the full press release, see: http://www.si2.org/?page=1285

At the Si2 conference several weeks back, TI announced that OpenDFM enables them to write 3x-20x fewer rules and substantially reduce rule deck complexity. TI observed as much as a 35x reduction in lines of code required with tests performed among 3 major EDA vendors, and proved that all check error counts matched the native DRC code exactly. OpenDFM uses a clever Tcl-based plug-in architecture that is fast and flexible, so additional functions and optimizations can be easily added in a modular fashion. Rapid commercial adoption by all major EDA vendors is anticipated.

So, what exists to help those who are now interested in adopting OpenDFM? There is a substantial amount of value-added “adoption collateral” that accompanies the OpenDFM standard, including an Installation Kit consisting of OpenDFM parser source code, contributed test cases, tutorials, and demonstration code for plug-ins. The parser not only helps companies get started immediately with OpenDFM (rather than attempting to re-create and re-code what already exists), but also helps support more consistent and interoperable adoption across the industry. There are nearly 30 real-world design test cases that DFMC members have shared during the process of developing and testing OpenDFM. There is also reference code that shows how to write a plug-in generator to automatically convert compact OpenDFM code into existing DRC formats (I anticipate that EDA vendors will be providing production plug-ins that generate the specific code used inside existing tools). Si2 has developed tutorials that can help new adopters understand OpenDFM, its features, and how to write rules using OpenDFM. This is particularly helpful when a company has rules that must be supported across different EDA vendors, each of which reads a different DRC format.

In addition to traditional physical DRC rules, OpenDFM includes a rich set of functions to make specifying conditional rules and advanced relationships more efficient, preserving “design intent” that is easier to understand and maintain. The OpenDFM spec even allows for inclusion of embedded images to explain a rule and it’s intent clearly and unambiguously (such as an explanatory drawing or SEM photograph). Advanced DFM checks are supported by utilizing DFM parameters and attributes defined by the DFMC members.

The press release also announces a Request For Technology (RFT) seeking new contributions for upcoming revisions of OpenDFM (see the URL above for details). I want to emphasize that the roadmap for OpenDFM supports electrical as well as physical limiters of effective yield, and as such can help unify the currently disparate array of miscellaneous non-standard file formats that today are not well correlated or synchronized, inviting risk of yield errors and difficulty maintaining them. One prime example is in parasitic extraction, where aligning the process description for use across industry parasitic extractors will add even more benefit beyond the traditional physical DRC realm.

If, like me, you believe that OpenDFM has the potential to be a major advance for physical verification of silicon, please help support this important effort. The full range of adoption collateral (e.g. Installation Kit) is available to all DFMC members. On behalf of the DFMC, we invite you to join them today, and help support this good cause as it continues to advance. Also, please remember that the OpenDFM standard is being made available, free of charge, from Si2’s website.