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ChipDesign Mag

Blogs

JB's Circuit

New Event Focuses on Semiconductor IP Reuse
blogger

Unique exhibition and trade show levels the playing field for customers and vendors as semiconductor intellectual property...

Chipnastics

Transitioning the Internet of Things to the Internet of Everything
blogger

By Dave Bursky, Semiconductor Technology Editor, Chip Design Voice biometrics to ubiquitous connectivity, this year's...

The Internet of Things

A VLIW Processor Bids to Dominate the Augmented Reality/Virtual Reality Market
blogger

By: Jonah McLeod If history is any guide to the future, each major next generation consumer device—PC, Smart Phone, and...

The Canonical Hamiltonian

Part II: The Ecstasy and the Agony of UVM Abstraction and Encapsulation Featuring the AMIQ APB VIP
blogger

Part II of our tour through UVM reusability through TLM ports and the factory in the AMIQ APB VIP. by Hamilton Carter...

Koby's Kaos

All Devices Eve
blogger

In some towns they call it Halloween, a time for kiddies in costumes to rot their teeth on bags of candy. Yeah, sure, just...

Pallab's Place

EUV and eBeam at SPIE ADV Litho 2013
blogger

While the main manufacturing flows are still focusing on optical lithography, eBeam and EUV are still making progress on...

Poll

Have you had CDC bugs slip through resulting in late ECOs or chip respins?
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Buyers Guide

 CHIP DESIGN BUYERS GUIDE 2008


{ Design Tools }
REGISTER TRANSFER LEVEL (RTL)
Actel Corporation
www.actel.com
Advanced RFIC (S) Pte Ltd
www.arfic.com
Altium - Making Electronics Design Better
www.altium.com
ASICS World Services, LTD.
www.asics.ws
Atrenta, Inc.
www.atrenta.com
austriamicrosystems AG
www.austriamicrosystems.com
Averant, Inc.
www.averant.com
Cadence Design Systems
www.cadence.com

Calypto Design System
2933 Bunker Hill Lane, Suite
202Santa Clara, CA 95054
(408) 850-2300 Telephone
(408)-850 2321 Fax
info@calypto.com
www.calypto.com

SLEC verifies that RTL implementations are functionally equivalent to systemlevel models. SLEC replaces time consuming simulation regressions by using system-level models written in C/ C++ or SystemC to verify RTL designs.

DeFacTo Technologies
www.defactotech.com
JEDA Technologies
www.jedatechnologies.com
Lattice Semiconductor
www.latticesemi.com
Magma Design Automation
www.magma-da.com
Matricus Inc.
www.matricsgroup.com
Mentor Graphics
www.mentor.com
Posedge Software Inc.
www.posedgesoft.com
Summit Design
www.summit-design.com
Synopsys, Inc.
www.synopsys.com
Synplicity, Inc
www.synplicity.com
Verific Design Automation
www.verific.com
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