Chip Design
IN FOCUS

Josh Lee sees maturity in the services niche

Click on Chip Design IN FOCUS now to Stay Informed
ChipDesign Mag

Blogs

JB's Circuit

Soft (Hardware) and Software IP Rule the IoT
blogger

By John Blyler, JB Systems Both soft (hardware) and software IP should dominate in the IoT market. But for which...

Koby's Kaos

Have Code – Will Exploit: Wire Beaverton
blogger

I heard the theme music whispering beneath the door even before the knock came. I opened it anyway. There he was¸ dressed...

The Canonical Hamiltonian

Listening to Meteors
blogger

The View from the Front Yard 3:30 AM, August 30, 2014 Texas A&M, hot on the heels of their newfound football...

The Internet of Things

IoT Gets Its Own Messaging Protocol Standard, MQTT
blogger

By: Jonah McLeod, Dir. of Corp. Mkt. Comm. at Kilopass Technology Inc. Anyone creating applications for the Internet of...

Chipnastics

Server system-on-chips pack up to 48 64-bit ARM cores
blogger

Targeting secure cloud servers, storage servers, compute servers, and data-plane applications, the ThunderX series of...

Pallab's Place

EUV and eBeam at SPIE ADV Litho 2013
blogger

While the main manufacturing flows are still focusing on optical lithography, eBeam and EUV are still making progress on...

Poll

Have you had CDC bugs slip through resulting in late ECOs or chip respins?
No
ECO
Respin
   
View Results

Affiliate Sponsors

Buyers Guide

 CHIP DESIGN BUYERS GUIDE 2008


{ Design Tools }
REGISTER TRANSFER LEVEL (RTL)
Actel Corporation
www.actel.com
Advanced RFIC (S) Pte Ltd
www.arfic.com
Altium - Making Electronics Design Better
www.altium.com
ASICS World Services, LTD.
www.asics.ws
Atrenta, Inc.
www.atrenta.com
austriamicrosystems AG
www.austriamicrosystems.com
Averant, Inc.
www.averant.com
Cadence Design Systems
www.cadence.com

Calypto Design System
2933 Bunker Hill Lane, Suite
202Santa Clara, CA 95054
(408) 850-2300 Telephone
(408)-850 2321 Fax
info@calypto.com
www.calypto.com

SLEC verifies that RTL implementations are functionally equivalent to systemlevel models. SLEC replaces time consuming simulation regressions by using system-level models written in C/ C++ or SystemC to verify RTL designs.

DeFacTo Technologies
www.defactotech.com
JEDA Technologies
www.jedatechnologies.com
Lattice Semiconductor
www.latticesemi.com
Magma Design Automation
www.magma-da.com
Matricus Inc.
www.matricsgroup.com
Mentor Graphics
www.mentor.com
Posedge Software Inc.
www.posedgesoft.com
Summit Design
www.summit-design.com
Synopsys, Inc.
www.synopsys.com
Synplicity, Inc
www.synplicity.com
Verific Design Automation
www.verific.com
EDAC EDAC GSA IEC OCP Si Subscribe Advertise About Us Contact Us