CHIP DESIGN BUYERS GUIDE 2008

{ Design Tools }

REGISTER TRANSFER LEVEL (RTL)

Actel Corporation www.actel.com

Advanced RFIC (S) Pte Ltd www.arfic.com

Altium - Making Electronics Design Better www.altium.com

ASICS World Services, LTD. www.asics.ws

Atrenta, Inc. www.atrenta.com

austriamicrosystems AG www.austriamicrosystems.com

Averant, Inc. www.averant.com

Cadence Design Systems www.cadence.com

Calypto Design System 2933 Bunker Hill Lane, Suite 202Santa Clara, CA 95054 (408) 850-2300 Telephone (408)-850 2321 Fax info@calypto.com www.calypto.com SLEC verifies that RTL implementations are functionally equivalent to systemlevel models. SLEC replaces time consuming simulation regressions by using system-level models written in C/ C++ or SystemC to verify RTL designs.

DeFacTo Technologies www.defactotech.com

JEDA Technologies www.jedatechnologies.com

Lattice Semiconductor www.latticesemi.com

Magma Design Automation www.magma-da.com

Matricus Inc. www.matricsgroup.com

Mentor Graphics www.mentor.com

Posedge Software Inc. www.posedgesoft.com

Summit Design www.summit-design.com

Synopsys, Inc. www.synopsys.com

Synplicity, Inc www.synplicity.com

Verific Design Automation www.verific.com

• Designing with FPGAs for Embedded Computing Speed and Flexibility

• SmartFusion2 Lowest Power FPGAs

• Kintex 7 FPGA family: High Performance DDR3 memory throughput achieved by optimization of the memory controller

• Write Assist in Low-Voltage SRAMs

• Enea Element®: Simplify Distributed Systems with Frameworks from Enea Element

• Redefining RF and Microwave Instrumentation Through Open Software and Modular Hardware

More White Papers >>

• Experts At The Table: Latency
• First Silicon At 14nm
• Tradeoffs On The Fly
• Editor's Note: Pushing The Limits
• Absolute Power: Apple’s Big Breakthrough

Sponsored by:

• Executive Outlook
• What’s Ahead For System-Level Design
• Adventures In Verification
• Editor's Note: Divide, Abstract And Conquer
• ESL Edge: Simple Economics

Sponsored by:

• Inside Leti’s Litho Lab
• Trickle Down Equipment Economics
• 3D NAND Market Heats Up
• Editor's View: A July Chill, Again
• Semico Spin: Painting By Numbers

Sponsored by:

• Chip Design Resource Catalog
• Chip Design Buyers' Guide
• Interoperability Guides
  • Cadence and Third-Party Solutions Guide
  • Mentor Graphics Vanguard Partner Interoperability Guide
  • OCP IP Member Guide
  • Synopsys - Focus on Interoperability
• IP Solutions Resource Catalog
• Valuable Resources
  • AdvancedTCA
  • DSP
  • FPGA and CPLD Resource Catalog
  • MIPS ® Embedded Resource Catalog
  • Multicore
  • PCI Express

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