CADENCE INTEROPERABILITY GUIDE

Power Forward Initiative Publishes On-Line Guide to Low-Power Design with the Common Power Format

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By: Susan Runowicz-Smith, Group Director, Cadence Design Systems, Power Forward Initiative

As the electronics industry moves toward advanced CMOS process geometries at 65nm and below, considerable power management challenges have emerged that cannot be met by a design infrastructure optimized for 90nm and above. Throughout the design and manufacturing chain, there is a clear need for a holistic power-aware infrastructure that will enable design teams; ASIC, library, IP, and tool vendors; equipment providers; and silicon foundries alike to efficiently produce lower power electronics. The existing design infrastructure has had shortcomings in holistically communicating power-related design intent across the design flow. These limitations have prevented companies from initiating complex low-power projects due to high levels of risk and unpredictable design costs. The Power Forward Initiative was formed to address these obstacles to lower power IC design facing the electronics industry.

In 2005, it was clear that power had become the most critical issue facing designers of electronic products. Advanced process technology was in place, power reduction techniques were known and in use, but design automation and its infrastructure lagged. Low-power design flows were manual, error-prone, risky, and expensive. The pressure to reduce power was ever more pervasive and the methodologies available were undesirable. Recognizing this burgeoning design automation and infrastructure problem, Cadence as the EDA leader took the initiative to tackle this crisis.

Within Cadence, technologists from over 15 business groups realized that to incorporate an efficient, automated low-power design solution into existing design flows would require significant innovation in every step of the design flow. Through intensive collaboration across the team, it was concluded that implementing advanced power reduction techniques could be best facilitated by a separate, comprehensive definition of power intent that could be applied at each step in the design, verification and implementation stages. The Common Power Format was born.

To solve the broader design infrastructure problem holistically, the effort had to involve the entire electronic product development design chain, including systems and EDA companies, IP suppliers, foundries, ASIC and design services companies as well as test companies. In May of 2006, Cadence teamed up with 9 other industry leaders – ARM, AMAT, AMD, ATI, Freescale, Fujitsu, NEC Electronics, NXP and TSMC-- to form the Power Forward Initiative (PFI). PFI’s collective aim is to link design, verification and implementation to reduce risk and increase predictability in chip power reduction. Members work to adopt a new automated design infrastructure aimed at reducing chip power consumption. The PFI members understood the urgent need for an automated, power-aware design infrastructure and joined together to validate an infrastructure based upon the Common Power Format (CPF).

The founding members of PFI worked together to refine and validate a holistic, CPF-enabled design, verification and implementation methodology. From the very outset, the goal was to quickly enable the rapid deployment of a design automation solution that comprehends power at every stage of the design process.

Starting in 2006, the founding companies of PFI reviewed and refined the CPF specification. They then initiated proof point projects that validated design flows using the Cadence® Low Power Solution with complex designs and power intent for these designs specified in CPF. By the fall of 2006, the PFI membership grew to nearly twenty companies. The ecosystem’s desire for a comprehensive low-power solution was evidenced by broader support of CPF across the design chain. Complex low-power design projects were underway at nearly all of the founding PFI member companies. IP companies began incorporating CPF into their implementation flows and leading foundries were busy readying reference flows based upon CPF-enabled methodology.

PFI members completed their work on the CPF specification in late 2006 and determined that CPF was ready for broad deployment and standardization. The CPF specification was contributed to the Silicon Integration Initiative (Si2) Low Power Coalition (LPC) in December 2006. In March 2007, after working through the LPC process, CPF 1.0 became a Si2 standard, freely available to everyone in the industry.

During the two years that the PFI members have been working on refining and validating a CPF-enabled design methodology, a wealth of experience was gained in the effort. PFI Members shared their design and methodology experiences at quarterly meetings, industry conferences and other public forums. At each meeting, those participating were impressed with the progress in bringing CPF-enabled methodology to the design community so quickly. CPF- enabled methodologies have been developed, refined and proven to not only reduce energy consumption but also dramatically reduce the time it takes to design and verify low power chips. It was clear now that our next project must capture this experience of the PFI members in one place for the global design community to share.

The work of the Power Forward Initiative members has resulted in A Practical Guide to Low Power Design – User experience with CPF. The Guide embodies the collective intellectual work and experience of some of the best engineers in the electronics industry. It focuses on practical design issues and address real-life design challenges including how to take advantage of advanced low-power design techniques—such as power shut-off, and dynamic voltage and frequency scaling— and describes how these techniques have been automated to ensure correct functionality and rapid design, verification and implementation.

Available free of charge from the Power Forward Initiative, the guide is divided into six sections: Introduction to Low Power; Verification of low-power Intent; Front-end Design; Low-Power Implementation; CPF User Experiences; and CPF Terminology Glossary. A Foreword by Dr. Alberto Sangiovanni-Vincentelli, The Edgar L. and Harold H. Buttner Chair of Electrical Engineering, University Of California, Berkeley, and Preface by Dr. Chi-Ping Hsu, Corporate Vice President, IC Digital and Power Forward, Cadence Design Systems describes the evolution of design that now must holistically address power consumption, and the vision behind the Power Forward Initiative. The guide illustrates the results of PFI members’ collaboration to accelerate the adoption and deployment of CPF-enabled design flows. It is published online and will be regularly updated to include more easy-to-read examples that can help designers get started reducing power consumption on their next design project.

The Power Forward Initiative includes AMD, Applied Materials, Alchip, ARC, ARM, Azuro, Cadence, Calypto Design Systems, Denali Software, Faraday Technology, Freescale, Fujitsu, Global Unichip, Globetech Solutions, Improv Systems, MIPS Technologies, NEC Electronics, NXP Semiconductors, Sequence Design, SMIC, Tensilica, TSMC, UMC, VeriSilicon, Virage Logic, and Vivace Semiconductor

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