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New White Papers
Evolving the Coverage-driven Verification Flow
Power Consumption at 40 and 45 nm
Accurately Analyzing Power in a Simulink Software Model-Based Design Flow
Capabilities to Maximize Productivity for FPGA Debug and Verification
Synopsys White Paper: Understanding the real cost of prototyping hardware
The PSP Model in RF CMOS Design
Blogs
Pallab's Place
Network ICs - packaging is a key design element
I recently had a chance to have a conversation with Judy Priest of Cisco about some of the design and packaging issues for...
Taken For Granted
DATE 2010 Preview
The Design Automation and Test in Europe 2010 conference will be held in Dresden Germany from March 8 to 12. DATE...
EDA Thoughts
Carbon Footprint is Good For ICs
IBM just demonstrated graphene transistors that could become a replacement for pure silicon-based ICs. | Photo...
JB's Circuit
Going Beyond and Returning to Reusability
Design for the Consumer Era is seen as the next iteration of the infamous Design-for-X paradigm shift by keynote presenter at...
Poll
• Cadence Interoperability Guide
CADENCE INTEROPERABILITY GUIDE
Articles
Power Forward Initiative Publishes On-Line Guide to Low-Power Design with the Common Power Format
As the electronics industry moves toward advanced CMOS process geometries at 65nm and below, considerable power management challenges have emerged that cannot be met by a desig ...
By: Susan Runowicz-Smith, Group Director, Cadence Design Systems, Power Forward InitiativeSolutions Listings
For e and SystemVerilog Development
AMIQ
Sentinel: Power, Noise, Reliability Platform for Chip-Package-System Co-DesignApache Design Solutions
ENOVIA Synchronicity DesignSync DFIIIDassault Systèmes
eInfochips releases highly configurable, URM compliant HDMI UVC for verification of HDMI compliant deviceseinfochips
Hummingbird®: Pushing the Limits of Cadence Applications and Exceed UsersHummingbird
MunEDA WiCkeD™: Improve Design Performance and YieldMunEDA
EDAConnect-SiPPerception Software
PLDA - Premier PCIe IP Products featuring Support for Cadence ToolsPLDA
Semiconductor IP SolutionsVirage Logic Corporation
- Experts At The Table: The Reliability Factor
- Verifying Low-Power Designs
- Low-Power Architectures Go Mainstream
- Editor’s Note: The Prius Wake Up Call
- Absolute Power: Fun Facts for the New Year
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