DAC Meanderings, 51st DAC 06_03
The day started early with the Accelera breakfast. The food was excellent. There were “Fluffy scrambled eggs”, bacon, sausage and a variety of pastries. For the first half hour or so folks straggled in, slowly orienting themselves after the first night of DAC parties. The proceedings kicked off with the handling of a few business issues. Shishpal Rawat, the current Accelera chairman outlined the achievement of the prior year and the goals and schedule of the ensuing one. The last order of business was the presentation of the Accelera Leadership Award for 2014 to Yatin Trivedi, (pictured).
A few moments later, Doulos’ John Aynsley, ever-spry, bounded onto the stage to introduce the members of his UVM roundtable.
John played devil’s advocate to keep the panel lively. He first asked what the members’ general feelings on System Verilog were. When all the panelists agreed that they were generally happy, John then prodded each of them to find out how happy they were, why, and what challenges they were still having. The general consensus seemed to be as follows:
- Asking designers to adopt object oriented class-based solution was a hard sale.
- Finally having a uniform standard offered by all the vendors was very, very nice.
- There were hiccups and burps along the way as internal libraries needed to be converted to the new standard and IP vendors tended not to have adopted the standard yet.
From the Accelera breakfast a brief walk brought me to the first time exhibitors’ interviews.
Marc Edwards, presenting for Silicon Cloud, described his vision of moving the engineering flow into the cloud. Allowing startups and others to avert the expense of large hardware box purchases. Silicon Cloud offers a solution that moves all design tools, licenses, and IP into a server space they maintain and monitor. The places 1000s of virtual machines at the disposal of design engineers who access the cloud via Chrome books that have been walled from the rest of the internet. All transactions that touch the design, IP, or tools are recorded. In addition to providing valuable information on the process flow and the usage of tools and IP, Silicon Cloud also watches for nefarious and/or non-conformal behavior with regards to the management of IP.
Larry Lapides presented Imperas’ services and product portfolio. The company is focusing on software verification in the embedded realm. Their portfolio of over 140 open access processor and peripheral models allows their customers to bring up their software ahead of design completion. The models run at millions of cycles per seconds allowing very comprehensive software scenarios. Automotive and medical embedded applications, where software failure is not an option, are adopting Imperas’ testing and system reliability tools and methodology.
Harnhua Ng presented Plunify’s FPGA-build optimizing solution. Their tool watches FPGA builds. which can take days to not converge, and provides early warning that non-convergence is imminent. The tool also points out the likely causes of the non-convergence within the design so that a successful build can be achieved next time. In addition to its dynamic build-watching features, the tool also has a static facility that scans the design-to-be-built and warns of known issues before the build begins.
Jason Png, OPTIC2connect’s founder and CEO, gave a brief presentation of his company’s optical interconnect prototyping services. He said they don’t intend to replace design engineers, just make their jobs much simpler. OPTIC2connect has helped their customers move their prototyping cycles for optically enabled bus infrastructures from six months to three weeks.
Synopsys is back in the Formal Verification Market
From a round of interviews with the new guard of EDA, I proceeded to an interview with one of the older names in EDA, Synopsys. Synopsys is announcing their new entry into the formal/static verification market at this year’s DAC. The all new tool introduces capabilities for formal verification, clock domain crossing, and low power static checking with other features on the way soon. The tool can load in chip level, fully-flattened RTL designs to facilitate proper low power and interconnect checking. It also sports simplified and compressed error output. Gone are the days of day long design checks followed by searching through gigabytes of data for the error that matters. The tool bundles errors up to their root cause which is reported along with the count of other errors that are attributed to the root. For those that sill want to get into the gory details for themselves, an API is provided for teasing every last bit of available data out of a formal/static verification run.
Jasper’s food truck party
Jasper brought three busloads of engineers and semiconductor industry aficionados to Treasure Island earlier today to partake of the delicious wares of five different food trucks.
Entertainment was provided by Rat-Pack styled musicians, a magician, a juggler, and a lawyer turned professional bubble maker.
A great time was had by all, and CEO Jasper CEO Kathryn Kranen, thanked the Jasper team for their excellent work.