• Gabe on EDA: Real Intent Helps Designers Verify Intent
• EDACafe: A Page is Turned
• Press Release: Graham Bell Joins Real Intent to Promote Early Functional Verification & Advanced Sign-Off Circuit Design Software
• Press Release: Real Intent Demos EDA Solutions for Early Functional Verification & Advanced Sign-off at Synopsys Users Group (SNUG)
• Article: Blindsided by a glitch

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• Photo Gallery

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• Parasoft approaches comprehensive testing for embedded software

  The explosive growth of portable and wireless technology is a driver for similar growth in embedded software development....

• Automating embedded software testing with Electric Cloud

  The problem comes in when you are not a software-centric company. The 2012 UBM Embedded Market Survey showed that, for the first time, QA engineers are becoming a significant portion of embedded software teams, and while the quality of debugging tools is still the top area for improvement, engineers seem to be getting more confident with what is available. However...

• Strategy And Technology: One On One With Wally Rhines

  Mentor's Chairman and CEO sounds off about where the IC design challenges are, what needs to be done to fix them, and what new opportunities will unfold.

• One-On-One: Jack Harding

  eSilicon's CEO talks with System-Level Design about changes in design at advanced nodes, the power of 2.5D and 3D stacking, and how the semiconductor supply chain is changing.

• One-On-One: Naveed Sherwani

  Open-Silicon's CEO talks with System-Level Design about getting the business priorities of designing a complex SoC in line with the technology; why getting chips out the door on time is critical and why it's not happening.

• Walter Ng, GLOBALFOUNDRIES at DAC 2011 - IP Talks presenter

  Interview with Walter Ng, Vice President, IP Ecosystem, GLOBALFOUNDRIES. DAC 2011. Demonstrating 32/28nm design, 20nm technology. Design Enablement, ChipEstimate.com IP Talks 2011

• Verification: What's in Your Wallet?

  This DAC Pavilion Panel explores technical and business issues related to SoC verification by panelists from ARM, AMD and Qualcomm.

• Open Text Interview
  Birgit Neil speaks on the need for Unix-based connectivity tools in EDA.

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• Grant Martin Presents at DAC 2010
• EDA Must Focus on Relentlessly Reducing Design Cost

• xACT 3D — A New Mentor tool for 3D Field Solver on IC Designs
• Day 0 at DAC 2010: “Let us compare Mythologies”
• GRID Sim Tech

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• Synopsys StarRC Custom 3D Extraction Gives 20X Speedup
• AMIQ Releases OVM to UVM Migration Wizard
• Mentor Verification Support for TSMC A/MS Flow 1.0
• Synopsys Unveils Galaxy Characterization Solution
• Methodics Design ProductIC Manages IP Data
• Celebrate 10 Years of Accellera Excellence at DAC
• AutoESL at DAC: High-level Synthesis for ASICs and FPGAs
• Collaboration Delivers 32/28nm HKMG Design Platform
• Magma Offers Free Trial of Titan Mixed-Signal Platform
• Companies Craft 65-nm Reference Flow for Low-Power
• Synopsys Acquires Synthesis Technology from Synfora
• TSMC 28nm A/MS Flow with Silicon F3D Extraction
• Cadence Methodologies Drive TSMC Reference Flow 11.0
• Mentor Solutions in Samsung 32nm High-K Metal Gate
• Five Tutorial Sessions by Domain Experts
• Synopsys to Acquire Virage Logic Corporation
• EVE: Looking Back on the Path Forward

• Bloggers and Journalists at DAC – Two Years Later

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• LTE-Advanced Signal Generation and Measurement Using SystemVue

• Linking Early Mechatronic System Analysis to Physical Testing

• Best Practice Development Processes for Medical Device FPGAs

• Direct Power MOSFET Capacitance Measurement at 3000 V

• Common Pitfalls in PCI Express Design

• Increasing Revenue Through Continuously Optimized Data Center Management

• Designing For Low Power

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• Power Model Complexity Grows
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• Editor's Note: Little Shifts, Big Changes
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• The Next SoCs
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• Editor's Note: Which Comes First?
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• Applied Tips Restructuring Plan in Solar and LED Units
• Micron Confirms Acquisition Talks With Elpida
• Microsoft to Join 3D TSV DRAM Consortium
• Editor's View: Training Technicians, Hudson Valley Style
• Semico Spin: Forecasting Wafer Demand: Technology Migration, Bottlenecks and Confetti

Sponsored by:

• Chip Design Resource Catalog
• Chip Design Buyers' Guide
• Interoperability Guides
  • Cadence and Third-Party Solutions Guide
  • Mentor Graphics Vanguard Partner Interoperability Guide
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  • Synopsys - Focus on Interoperability
• IP Solutions Resource Catalog
• Valuable Resources
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  • DSP
  • FPGA and CPLD Resource Catalog
  • MIPS ® Embedded Resource Catalog
  • Multicore
  • PCI Express

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