As the System-on-Chip (SoC) design style becomes popular, more design starts are mixed-signal. According to a review by IBS Corp 2003, 73% of SoC design starts will be mixed signal by 2006. This has led to new challenges in SoC design and verification. Digital-centric designers suffer due to insufficient modeling and simulation accuracy for analog circuits. Analog/RF-centric designers, such as wireless communication system designers, suffer due to insufficient simulation speed for architectural exploration and verification, design corner validation and regressions. Shrinking time-to-market windows and the growing size and complexity of designs are making it difficult for designers to continue using current methods from both top-down digital design flows and bottom-up analog design flows. To solve these problems, many design companies adopt new methods to create a mixed-signal top-down design flow.

Advantages of mixed-signal behavioral modeling and a top-down methodology are discussed by number of authors, but most fall short of suggesting how to gain maximum benefits. Behavioral modeling has great potential for faster and better mixed-signal system verification, but using abstracted models without properly understanding their impact diminishes their effectiveness. Adopting behavioral modeling can be costly in terms of time and resources spent to train developers, not to mention the actual development and verification of models. It’s important, then, to understand how to maximize benefits.

Figure 1 shows a typical top-down design flow for mixed signal designs. Analog behavioral models are used at the top of the design process, along with RTL, to establish system-level behavior. Designers verify the system using these models, validating the mixed-signal architecture early in the design process, thus minimizing potential problems downstream. Then, functional blocks are translated into transistor level designs. Here, designers can perform system regressions at any time by using transistor level implementation for some blocks while retaining other blocks at higher abstraction levels, making the simulations faster. Once the transistor level blocks are verified, layouts are created and post-layout simulations are done. Analog behavioral models are recalibrated against the transistor level implementations using post-layout data.

Figure 1: Top Down Mixed Signal design flow.

A methodology is required on how behavioral modeling should be used during mixed-signal simulation. The following section talks about factors affecting simulation performance. Finally, the “Experimental Results� section illustrates a case study, using a phase-locked loop, where we show that good selection of behavioral models gives dramatic performance improvement, yet improper choices actually lead to performance degradation. Finally, we present guidelines on how the behavioral models should be used.

Factors affecting performance

In order to understand how performance can be impacted, we must also understand the general principles of SPICE simulation. Two important algorithms in SPICE include matrix solving and timestep control.

SPICE simulators, such as the Eldo engine within ADVance MS, represent the circuit in GV=I matrices, including non-linear semiconductor devices such as transistors (non-linear devices are linearized before being “stampedâ€? into the matrices). Changes in voltage or current sources, bias points, or other circuit conditions perturb the matrix and require the system to be re-solved. Smaller matrices are quick to solve, but since matrices grow O(n²), the expense of solving larger matrices is invariably superlinear.

While SPICE circuits are continuous-time systems, software simulators and computers are discrete computational systems. In order to bridge this gap, simulators typically use dynamically varying sampling points, commonly referred to timepoints, and the circuit matrices are evaluated at each timepoint. The space between timepoints (“timesteps�) varies in order to optimize performance; depending on set of criteria, the simulator predicts either a longer or shorter “next� timepoint. Circuits with relatively slow transitions or switching activity have larger timesteps, while rapid circuit activity suggests smaller timesteps. SPICE simulators use a “global� timestep mechanism, where all parts of the circuit are evaluated synchronously.

The simulation speed of any circuit is proportional to the number of SPICE components in that circuit. More components mean more time is needed to complete the simulation. Normally, if a component is replaced by its behavioral model, the number of SPICE components drops, thus reducing the overall simulation time. However, simulation speed also depends on some other factors, like switching activity.

Another important factor that affects the simulation speed during transient analysis is the switching activity of components. Like the number of components in a simulation, increasing (faster) switching activity leads to longer a simulation time. A smaller component that has a higher switching activity can take more time to simulate compared to a large circuit that has barely any switching activity; simulation performance is simultaneously related to both the number of circuit elements and switching activity.

Furthermore, since most SPICE simulators represent the whole circuit as a single large matrix, at every time-point the whole matrix has to be solved to compute the values. If a small part of the circuit is causing a lot of switching activity, it is going to reduce the time-interval between the time-points. However, since the matrix includes other larger blocks as well, it will now have to be solved at these smaller intervals, increasing the simulation time.

In a mixed signal design, A/D and D/A boundary elements are involved in full chip simulation. During simulation, these elements act as communication channels between analog and digital components. They are necessary overhead when joining electrical domain entities (analog) with signal domain entities (digital).

Generally, behavioral models make simulations much faster, compared to SPICE models. But there is a trade-off between performance and accuracy. Highly accurate models usually require significant development effort, and complex models take longer to simulate compared to simple ones.

Behavioral models used to improve system verification speed should correlate well to the circuit implementation. Model development methodology must include comparisons against the original circuit.

Experimental Results

A 240 MHz phase-locked loop with an input frequency of 60 MHz as shown in Figure 2 is taken as a case study.

Figure 2: This is a block diagram of a high-frequency PPL circuit.

All simulations were performed on a 3.4 GHz processor with 1.0 GB of RAM. The phase detector and the prescaler are digital blocks, and charge-pump, filter and voltage-controlled oscillator are analog components of the design. Behavioral models are developed using VHDL-AMS, VHDL, Verilog-AMS and Verilog. We use different combinations of SPICE and behavioral models to run circuit simulations. Some of the experimental results are shown in Table 1.

As a base-line for comparison, the all-SPICE simulation takes 26 min 56 s of CPU time. From that, we replace various blocks in the PLL circuit with behavioral models.

When we replace the phase detector with Verilog code, the CPU time reduces by 16%, but the number timesteps actually increases by 0.5%. The phase-detector contributes little switching activity to the system, but it represents 10% of the total SPICE component count. The behavioral model leads to slight increase in the switching activity, though overall, the component reduction has a larger effect.

The charge-pump circuit is an analog component that takes digital inputs (voltages and currents representing logical states) from phase-detector circuit and provides an analog output to the filter. By replacing charge-pump by its VHDL-AMS model, the number of SPICE components reduces by 4.5%, while the simulation time actually increases by more than 2%.

The charge-pump is only 50 components, constituting 4% of the entire design. The output of the charge-pump is also very smooth, i.e. the charge-pump doesn’t contribute much to the overall switching activity. Since the charge-pump has neither many components nor switching activity, replacing it actually increases overall simulation time, due to the intrinsic overhead of simulating a behavior model combined with how the model is implemented.

The behavioral model for the charge-pump uses digital inputs (digital states instead of voltages and currents), switching between multiple simultaneous equations to describe its analog output. However, changing simultaneous equations can cause discontinuities in the analog solver. In turn, these discontinuities result in timepoint rejection, forcing the analog engine to reduce its timestep sizes. Therefore, it takes more time to finish the entire simulation, compared to using the schematic charge pump.

When we replace the VCO by its behavioral model, the number of components drops by approximately 65%, and simulation performance improves by nearly 40X. We find that most of the switching activity of entire system is due to the VCO, since the number of timesteps reduces by 78%.

Figure 3: This plot illustrates the SPICE VCO output waveform of a VCC.

Figure 3 shows a portion of the output waveform when simulation was done using a SPICE VCO. The transition shows numerous timepoints. This VCO is a ring oscillator. Within the VCO, each stage transitions slightly out of phase with the others. Since Eldo uses global timepoints, all other stages are evaluated at the same time, leading to a multitude of closely spaced timepoints.

Figure 4 shows the same waveform but with a behavioral VCO. Comparing it against Figure-3 clearly illustrates the reduction in timepoints. The behavioral VCO uses equations to derive its outputs, with no intermediate oscillator stages like the schematic VCO. Therefore, few intermediate timepoints during transitions are needed by the simulator.

Figure 4: Here, the behavioral VCO output waveform is shown.

Replacing the phase detector and the VCO circuits with behavioral models drops the CPU time from 1,616.80 s to 30.56 s, a performance improvement of 53X. On the other hand, swapping the prescaler, instead of the phase detector, results in an additional 2X speed-up, down to 12.53 s. The two circuit configurations have nearly the same number of components (less than 10% difference), however.

The better performance in the second case is because the VCO outputs directly into the prescaler using a digital connection. The VCO’s output and the prescaler’s input are digital signal data types, so ADVance MS does not have to convert the VCO output into an analog voltage and current, and the digital interface is preserved. In contrast, in the first case the VCO’s digital signal output has to be converted into an analog waveform before entering the prescaler circuit. The conversion of a signal into an analog waveform is itself an overhead. The VCO’s fast output compounds the problem by forcing correspondingly rapid D/A conversion, generating more timepoints compared to the second case.

When we replaced all the blocks by behavioral models, except the VCO, the total CPU time reduces by only 26%. The VCO had the highest number of components, over half, and also generated the most of the circuit activity.

Replacing all the blocks by behavioral models gave a performance improvement of 99.9%, more than 900X faster than the original circuit configuration.

Table 1: Here are the experimental results of the PPL case study.

Guidelines to improve performance

From the experimental results in section 4, we see that when a component with significant switching activity is replaced by its behavioral model, we have great improvement in simulation speed. Replacing smaller components with small amounts of switching activity may not give faster performance, and in one case, it actually results in a reduction in speed.

We then form these guidelines:

1. Large blocks with high component counts should be the first candidates for replacement with behavioral models.
2. Keep interfaces between circuit blocks digital when possible. Calculating a digital event is much cheaper than calculating a SPICE timepoint.
3. If two blocks have almost an identical number of components, replace the block that has more switching activity.
4. If a block has very few components, and it doesn't create much switching activity, it';s probably not worth replacing it with a behavioral model.

While not necessarily a technique for performance improvement, behavioral models should be calibrated or validated against the transistor level implementation to make them accurate enough for the simulations to make sense.

Even though use of behavioral analog/mixed signal modeling has increased, methodologies to maximally utilize their potential are still missing. Using a design example, we have shown that when a large block with high switching activity is replaced by a behavioral model, we achieved dramatic performance improvements. In the other case, when a smaller block with smoother response was replaced, it actually led to performance degradation. Best utilization is achieved in verification by paying attention to these issues and guidelines.