The nature of semiconductor intellectual property (IP) has evolved significantly over the past decade. It has moved from basic building-block components, such as phase-locked loops (PLLs), standard cells, and library generators, through larger functional blocks like central processing units (CPUs) and digital signal processors (DSPs). Today, the focus is on "killer functions" ranging from MPEG decode and audio processing to wireless data. Just last year, the average application-specific integrated circuit (ASIC) contained 21 IP blocks. Of those blocks, 60% came from external providers. This trend presents a significant challenge to the system-on-a-chip (SoC) designer. He or she is tasked with designing for the integration of multiple, disparate IP cores while being able to adequately verify that all of that IP gets connected properly. How well the designer addresses this challenge will ultimately impact the success or failure of the SoC project.
Luckily, the IP climate is changing. New options are available to the SoC engineer, such as the use of proven IP from other semiconductor companies. Large semiconductor companies are feeling strategic pressures to make both chips and IP available. Although a few of them do license out IP, most don't have the volume to justify a dedicated IP sales and support operation. For those semiconductor companies that don't license out IP, new IP commercialization services are available to make that proven IP available to other SoC designers.
To better comprehend the magnitude of the challenge facing today's SoC designer, it's important to first realize what's going on with chip design in general. According to a recent iSuppli study, there were 3500 design starts in 1998. Today, there are only about 1800 (see Figure 1). This drop in design starts has many EDA and IP companies wringing their hands. Yet engineers around the world should be proud that they're delivering far more than ever before. While design starts have been going down, the number of gates per chip has been rising exponentially with Moore's Law. Multiplying design starts by gates per design predicts that 15.2 billion gates will be placed by designers worldwide in 2007.
Thanks to a survey conducted by EE Times, it's possible to explore what these statistics mean for chip designers. According to the survey, there were an average of 8.4 million gates per ASIC in 2005. The typical team had 13 engineers and teams averaged 1.2 projects a year. In 2005, each engineer was therefore responsible for 775,000 gates. Given that the average ASIC is expected to exceed 14 million gates in 2007, the gates per engineer will have to jump to 1.3 million a year. The old industry rule of thumb, which dictates that an engineer can design 50 gates a day from scratch, yields less than a hundredth of the required productivity.
Figure 1: Although design starts are down, the total value that engineers deliver continues to grow exponentially (source: IPextreme).
SoC designers can obtain some linear improvement in design productivity through the use of higher-level tools and electronicsystem- level (ESL) flows like SystemC. But this improvement will clearly not be sufficient. The only solution is a deeper embrace of what has been working best over the last couple of years: massive design reuse from both internal and external sources.
The use of IP is already the industry norm and it appears to be the logical answer to this dilemma. Yet recent trends seem to indicate that IP companies are dying out (see Sidebar, "A Lesson from History"
). In the late 1990s, for example, there were over 400 semiconductor IP companies. Today, there are only about 150. In reality, the perception that the IP industry is dying out may be nothing more than just a sign of the supplier consolidation that's typical in new industries. This fact is confirmed by the EE Times survey, which found that the first place that designers look for new IP is existing suppliers. Today, IP companies have consolidated themselves into three camps: pure-play IP (e.g., ARM and Rambus), EDA (e.g., Synopsys, Mentor, and Cadence), and design-services companies.
Figure 2: Technology-licensing firms work to connect IP to customers. They take designs from semiconductor companies, package them with complete deliverables, and support their integration by a range of end customers (source: IPextreme).
While this IP consolidation is going on, another trend has emerged. Integrated device manufacturers (IDMs) are no longer differentiated by their fabs. With 60% of integrated-circuit (IC) content coming from other companies, differentiation is instead coming at the system level (even if only on one chip). The skill and ability to rapidly assemble IP (including software) has become paramount. To satisfy this voracious IP appetite, large semiconductor vendors are feeling strategic pressure to offer their internally developed IP to other chipdevelopment companies. Further pressure arises from the desire to see their technology adopted as the industry standard. These semiconductor vendors typically have good and proven designs. Yet few of them know how to package and sell their technology as IP. In addition, even less want their engineers supporting it.
A BETTER ALTERNATIVE
There is a way to deal with these industry challenges while giving the SoC design community all of the IP subsystems that it now demands. The answer lies in the migration of the large semiconductor company into the IP space--possibly facilitated by a technology-licensing partner that acts like a value-added IP reseller. Working with semiconductor companies, the licensing company can deliver the semiconductor company's IP and make it readily available for use by the SoC design community (see Figure 2). This move makes sense--especially given that according to iSuppli, the IP market is expected to grow from $1.4 billion in 2005 to $2.7 billion in 2010. In addition, the complexity curve is going to soon cause many independent IP providers to "hit the wall." Note also that what many semiconductor companies offered four years ago as a whole chip is now the perfect size to be reused as an IP core (see Figure 3).
Figure 3: What was a complete 180-nm chip in 2001 is the right size for IP at 90 nm. As process technology enables it, system companies must integrate peripheral chips to remain competitive (source: IPextreme).
Some semiconductor companies have opted to try to package and sell IP themselves with limited results. All too often, the volumes haven't been high enough to justify the internal expense of this undertaking. This is where an IP-licensing company comes into the picture. It partners with large semiconductor companies to implement a strategy to increase chip sales through IP licensing. The IP-licensing company then licenses this silicon-proven IP to customers. It packages it for easy integration and handles all of the necessary sales, marketing, and support.
For the semiconductor company, this approach brings a multitude of benefits over and above allowing it to sell more chips. It also allows the semiconductor company to sell companion chips, provide a second source, promote technology leadership, and retain customers that are going to ASIC. In other words, it allows semiconductor companies to keep customers. If system companies don't integrate peripheral chips when process technology enables it, they'll lose to competitors who do perform such integration. If the IP of a peripheral chip isn't made available, customers will go elsewhere. Offering the IP therefore retains customers while blocking competitors. In addition, IP solves end-of-life issues by enabling production life beyond the initial fabrication-process life.
It's interesting to examine this approach versus the lifecycle of a design. Early in the lifecycle, licensing IP can provide the semiconductor company with a way to help accelerate the market adoption of new technology. Freescale realized this benefit with its FlexRay advanced automotive network technology. Though anyone is free to implement to the FlexRay spec, it would take at least 30 good engineers a couple of years to complete this process. Freescale has several chips with FlexRay interfaces on the market. Yet it knows that those chips won't sell in volume until there are other FlexRay devices, such as sensors and actuators, with which they can talk. Instead of waiting two or three years for others to implement FlexRay, Freescale opted to make its design available through IPextreme. In doing so, it hastened the standard's adoption.
Different benefits arise in other design-lifecycle phases. In the middle, IP can help to enlarge the chip ecosystem for anything that runs code, such as a processor. It also can build the brand and open the technology for use in new markets. At the end of the lifecycle, IP provides the semiconductor company with a way to extend the life of a design far beyond the original chip production run. It therefore garners a large return on the engineering investment. In addition, it can help customers deal with chip end-of-production issues.
For the SoC design customer buying this IP, the benefit is obvious. There is simply no way that the customer can design today's highly complex, high-gate-count chips from scratch. Massive reuse of proven IP offers such customers a quick, easy, reliable, and lower-risk way of dealing with this challenge.
The electronics industry is now facing a serious challenge. Design complexity is on the rise and SoC designers are being forced beyond their productivity limits. With massive reuse of reliable IP from a trusted source, they can possibly ease the design burden that they now face. More and more, such IP will come via collaborations between semiconductor and technologylicensing companies. Though many IP companies have failed, IP business is booming. Moreover, the IP and semiconductor industries should no longer be considered as separate. IP is simply becoming an ever-important part of the semiconductor industry.