Published on March 23rd, 2007

DFM and DFY: Old Solutions to New Problems

The semiconductor industry's shattered supply chain must be reintegrated, replacing clever point solutions with holistic and economical flows.
Design for manufacture (DFM) for semiconductors has risen from relative obscurity to near-cult status. Anyone attending recent Design Automation Conferences couldn't avoid DFM in booths, papers, panels, and presentations. And who would have imagined that we'd see semiconductor equipment companies exhibiting at DAC and EDA companies at SEMICON-all talking about the same subject? DFM articles (like this one) abound in design journals, semiconductor magazines, web sites, newsletters, etc. Numerous well-funded DFM startups are seeking market traction. They also are beginning to be acquired at significant premiums.

The focus on DFM coupled with the arduous 130-nm ramp of a few years ago catalyzed an analogous focus on design for yield (DFY). Were the poor yields experienced in fabs ramping 130-nm processes due to "lithography-insensitive" designs, which had minimum feature sizes that were being printed at about half the wavelength of the exposure source? Or were they primarily a consequence of the simultaneous ramping of copper and low-k dielectrics? The continuing focus on the economic implementation of Moore's Law demands that these issues be addressed in order to determine how to best approach the impending 65-nm ramp. Yet this much seems clear: The days of easy scaling driven by above-wavelength lithography and the economically convenient separation of semiconductor design and manufacturing are over.

With its popularity, numerous definitions of DFM have emerged. Mark Rencher, CEO of Pivotal Enterprises, has authored an extensive series of DFM articles. He offered the following definition of DFY as contrasted with DFM: "DFY is the management of the design's sensitivity to the manufacturing process, while DFM is the management of technology constraints (rules, lithography) applied to a design."

Although DFM may look new to the semiconductor industry, it has a long and storied history. According to Vincent Chan and Filippo Salustri, "[a]lthough the term Design for Manufacture (DFM) is relatively new, the principles of DFM originated more than 200 years ago." Chan and Filippo liken the principals of DFM to eighteenth-century American inventor Eli Whitney's revolutionary concept of manufacturing with interchangeable parts. That concept streamlined the production of muskets from highly individualized, artisanal, and expensive to standardized, mechanized, and inexpensive. Continuing to trace the historical ties of DFM, Chan and Filippo note the impact of Henry Ford's extensive implementation of the assembly line, which transformed the automobile industry. Henry Ford said this about the Model T: "The important feature...was its simplicity. All components were easily accessible....It was up to me, the designer, to make the car so completely simple....The less complex the article, the easier it is to make, the cheaper it may be sold." These principals form the basis of DFM.

Ford gained this efficiency by studying parts and simplifying and designing the machines to make them. What was common sense to Ford would today be characterized as DFM by semiconductor engineers. Although the term DFM didn't come into widespread use until the mid-1980s, its principles were first formally defined in a series of articles by Roger W. Bolz. Those articles were originally published in 1947 as a book titled, "Production Processes - The Productivity Handbook." They have been revised many times since then.

In the past, DFM seemed more appropriate for assemblyoriented manufacturing, where the emphasis is on reducing labor costs and improving throughput. If one accepts Rencher's definition, the semiconductor industry's focus might be better placed on DFY. Companies with $3-billion wafer fabs operating at low yields won't be in business very long. Time-to-market demands-particularly in consumer markets-reward the first company that can fill the pipeline with high-volume, highperformance devices. At the same time, dramatic increases in design and photomask costs continue to reduce the number of new designs. Consequently, semiconductor companies must make larger bets on fewer products. They therefore place a heavy premium on a successful ramp.

Why is this most complex of industries only now seriously addressing DFY? Interestingly, DFY behaviors weren't uncommon (if only ad hoc) in the early days of the semiconductor industry. Designers and fab engineers were often in the same building if not adjacent cubicles. Chris Mack, lithographerextraordinaire and the inventor of Pro-Lith, the gold standard in lithography simulation, noted, "In the very early days of the industry, you had to lay out the transistors with the manufacturing process in mind. And it was only the abstraction of design outside of manufacturing, through the use of design rules, that really enabled the growth of design as its own important contributor to the industry. However, today, design rules have become inadequate to describe the manufacturing reality and its impact on the design process." The challenges associated with ramping new nodes to acceptable yields grew despite ever-increasing numbers of design rules.
The emergence of DFY was affected by two factors. The first one was the emergence of sub-wavelength lithography when the industry moved to 180-nm design rules using 248-nm light (see Figure A). Before sub-wavelength lithography, lithographers were metaphorically painting a 3-in. line with a 1-in. paintbrush. This approach resulted in a more what-you-see-is-what-you-get (WYSIWYG) world. Designers could generally realize their elegant, rectilinear designs on silicon-albeit with somewhat rounded corners.

Figure A
Figure A: Trends in lithography are depicted here.

For two decades, the death of optical lithography had (and has) been forecasted. It is always to be replaced some five years from the date of the forecast with a "finer paintbrush" (at various times, X-rays, electron beams, ion beams, etc.). For reasons too numerous to cover here, however, lithographers have successfully extended optical lithography. Today, sub-wavelength lithography has progressed to painting a 1-in. line with a 3-in. paintbrush, which can result in significant pattern distortion. As 193-nm lithography is extended to 65-, 45-, and 32-nm design rules, pattern distortions increase. These pattern distortions can affect device performance and yield, requiring more and more aggressive compensations. Indeed, these distortions now have a more profound effect on yield than the traditional culprit, random particle defects (see Figure B). The second reason for the slow emergence of DFY was the difficulty of developing and implementing the methodologies in a disaggregated industry. In two decades, the semiconductor industry moved from near-total vertical integration, when semiconductor design and manufacturing were typically co-located, to neartotal disaggregation. The supply chain was split into hundreds of pieces. This disaggregation culminated in the complete cleavage of semiconductor design and manufacturing with the advent of fabless and foundry companies. It overwhelmed any single company's ability to comprehend the entire process. A legacy of this decades-long disaggregation was the so-called tall, skinny engineer-steeped in knowledge of his field, but perhaps less familiar with what happens upstream and unaware of the potential downstream impact of his choices. Solving problems by squeezing the proverbial balloon often moves the problem downstream.

Figure B
Figure B: This graphic depicts defect-driven versus feature-driven yield. Source: PDF Solutions

With the advent of foundries, the old maxim, "Real men own fabs," fell into disfavor. Foundries and fabless companies have been growing faster than the semiconductor industry as a whole. Recently, however, industry pundits have begun to question which model is better suited for the new millennium. With their long tradition of both design and manufacture, the older, larger, integrated device manufacturers (IDMs) may be better equipped to address the daunting DFY challenges waiting at 65 nm and below. Many of these companies, which were once highly vertically integrated, retained senior managers with diverse experiences.

Fabless companies, on the other hand, thrived by a laser-like focus on the differentiated design of devices with unique performance and/or functionality. The challenge for fabless companies is to figure out how to compete with these IDMs with regards to achieving the many benefits of effective DFY implementation. Larger fabless companies are building manufacturingliaison organizations, which are staffed with engineers with lithography and manufacturing experience. Foundry companies are expanding their business models and adding a variety of complementary design skills and tools. They're moving away from pure manufacturing.

Acknowledging the particular challenges facing fabless companies, Shankar Pennathur, Director of Technology and Logistics for the fabless semiconductor company, Centillium Communications Corp., noted, "DFM is not merely a buzzword right now; it is reality in today's deep-sub-micron chip designs. For the 90-nm process node, DFM is not a luxury; it is a necessity for (chip) survival. For the typical smaller to medium-sized fabless company located in Silicon Valley, Taipei, or Tel Aviv, the necessary expertise and manpower to execute a complete 90-nm design that meets aggressive performance requirements-while simultaneously meeting unforgiving market window realities for product launch-may unfortunately simply not be there."

IBM is an example of a company that has resisted disaggregation and continues to leverage vertical integration. IBM has a history of developing materials, equipment, and design tools, which it has successfully leveraged into a position of technology leadership. The company's entry into the foundry business placed it in a unique position to contrast its ability to execute DFY on internal versus external application-specific integrated circuits (ASICs) and systems-on-a-chip (SoCs). IBM's Vice President and General Manager of the ASIC division, Tom Reeves, reported that IBM's internal designs at 130 nm had a 95% first-pass success rate compared to a 5% rate for third-party designs. With the average design submitted to IBM requiring 2.5 re-spins, the mask costs alone can run into the millions of dollars.

The ultimate solutions to the DFY and disaggregation challenges will likely be found in the following: reintegration, new and more aggressive forms of collaboration, and the EDA industry's ability to encompass lithography and manufacturing intelligence into its products. Some believe that the implementation of restrictive design rules (RDRs) represents another solution to the DFY challenge. According to Gartner Group, "[a]dopting RDRs will enable designers to use less expensive layout tools and decrease the use of DFM and yield analysis tools..RDRs will also require bridging the `disconnect' between chip makers and EDA companies."

There are several examples of semiconductor companies rethinking their business models. AMD recently acquired ATI, one of the world's largest fabless companies. Jackson Hu, CEO of UMC-the world's second-largest foundry-noted, "[t]he leading foundries in this age must have the capabilities of an integrated device manufacturer." Freescale abandoned the Crolles Alliance and joined the IBM/Samsung/Chartered "Common Platform." Micron Technology constructed an internal photomask operation, apparently reversing over a decade of captive-to-merchant transitions. These are significant steps in the process of rethinking the industry structure and value chain that have dominated for the past two decades.

Moore's Law may continue to provide the engine to drive the electronics industry to $2 trillion. Whether or not this materializes will depend largely on economics-not technology. Scaling and larger wafers have been the principal drivers for "smaller, faster, cheaper" and the low-hanging fruit is pretty well tapped out. The semiconductor industry's shattered supply chain must be somehow reintegrated, replacing clever point solutions with holistic and economical flows. Open collaboration must become a way of life-not a marketing slogan.

Three-billion-dollar wafer fabs cannot ramp new technology nodes for months at low yields because design and manufacturing were unable to bridge their gap. Designers cannot simply point the finger at fab managers and vice versa. Technology integration and yield will separate the winners from the losers. Like Mark Twain, reports of the death of semiconductor manufacturing as a differentiator may be greatly exaggerated. Leading-edge semiconductor manufacturing-effectively integrated with manufacturing-sensitive design-will be a critical element of success in the 21st century.
Ken Rygler is the President of Rygler and Associates Inc., a high-tech consulting firm focused on "Bringing Technology To Market." Prior to starting Rygler and Associates in January of 2002, Rygler was Executive Vice President of DuPont Photomasks, a company he founded in 1986 and took public in 1996. Before retiring from E.I. DuPont de Nemours in 1996, Rygler held numerous seniorbusiness- management positions in a variety of businesses in the electronics, industrial, and consumer markets. Rygler graduated with Honors from Bethany College (WV) in 1964 with a major in chemistry and a minor in economics. He was an officer of DuPont Photomasks, a member of the board of directors of DuPont Dai Nippon Engineering and DuPont Photomasks Taiwan Ltd., and served on the board of the American Electronics Association/Texas. He is currently an officer on the board of directors of the Austin Symphony Orchestra, Petersen Advanced Lithography, and serves as Acting CEO of Pixelligent Technologies.

REFERENCES:
Mark Rencher, EE Times, March 24, 2003.
Henry Ford, “My Life and Work,? 1922.
Vincent Chan and Filippo Salustri, Overview of DFM, Ryerson University, 2003.
Chris Mack, Semiconductor International, July 1, 2004.
Shankar Pennathur, Silicon Strategies, September 22, 2004.
Gabe Moretti, EDN, April 1, 2004.
EETimes, July 26, 2006.
EE Times, October 4, 2005.

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