Modern integrated-circuit design methodologies and advanced process technologies can produce complex mixed-signal devices. These devices, which are known as systems-on-a-chip (SoCs), feature a large number of digital, analog, and RF cores on a single chip. Such devices integrate complex digital cores with analog functions in single-chip SoCs. Their goal is to address the need for higher performance and richer functionality. SoC designs are commonly used for market-leading applications in multimedia, wireless, telecommunications, and a wide variety of other consumer applications.

In a large mixed-signal system, the interaction between several digital and analog blocks must be verified for correct system-level performance and functionality. Designers of individual blocks may overlook some interface or algorithmic issues between blocks. Usually, such an oversight arises because system-level design specifications are difficult to consider during individual-circuit design. As a result, interface issues will almost always occur. The top-level SoC verification of digital, analog, and RF blocks can ensure system performance and validate design functionality between the integrated-circuit blocks.

Many aspects of a design must be taken into consideration when attempting top-level verification. They include the following:

• System power-up and power-down sequences
• Analog-to-digital (A/D) and digital-to-analog (D/A) interfaces
• Drive-load interface functionality
• The effects of different voltage domains in logic and analog sections
• The impact of layout parasitics

Without adequate top-level-verification methodologies and coverage, errors can easily go undetected. The result is costly chip re-spins. According to several Synopsys user surveys, a chip re-spin is most often due to functional errors (see Figure 1). With the average cost of a mask re-spin at $1M+ for 90-nm and below processes, achieving first-pass silicon success is an essential requirement for SoC design teams. Traditional circuit-simulation and verification methods focus on separate analog and digital design flows. They don’t provide adequate top-level verification.

Figure 1: According to a recent survey, functional errors are the main cause for chip re-spins. (Source: Synopsys 2004 user survey)

Often, the blocks to be integrated are designed and verified individually with different levels of abstractions ranging from RT, gate, and SPICE to analog behavioral models. Hence, an ideal top-level verification tool must be able to accept those different levels of design abstraction. The complexity of SoC verification challenges both the ability of traditional chip-verification methodologies and EDA tools. Increasingly, IC design teams are therefore turning to more comprehensive top-level circuit verification and regression approaches to improve their design’s overall cost of results (COR).

Analog And Digital Worlds

A traditional verification flow allows analog designers to work within their own world while digital designers work within a separate set of tools. The digital parts of the design are verified in an RTL/synthesis environment. Meanwhile, the analog components are verified in a circuit-simulation environment. With these teams working independently of each other, there is no full-chip integration verification of the mixed-signal SoC. To account for potential integration issues, assumptions are made in the testbenches. In addition, sufficient guard-banding is provided around the analog block to isolate digital noise from the sensitive analog substrate. With more complex functions integrated on the chip and increasing on-chip clock frequencies, however, guard-banding is no longer an option. It cannot fully account for the functionality embedded within the analog blocks. Additionally, it is too costly to waste silicon/die space--especially for the high-volume SoCs for consumer applications.

During the design cycles, cell- and block-level static and dynamic timing are usually characterized extensively. Because timing is critical to digital circuits, care must be taken to contend with clock skew, race conditions, meta-stability, and setup/hold requirements. These performance factors are simulated in a digital simulation environment. During analog block authoring, attributes like propagation delays, power-up and power-down times, and detailed timing and power consumption must be verified. With separate verification flows, however, the system-level block timing cannot be verified for mixed-signal systems in which the analog and digital blocks have timing dependencies.

Some design teams use a Verilog behavioral model to mimic the behavior of an analog function (see Figure 2). In this case, top-level simulation is completed using a rough estimation of the analog sections and a high-level description of the digital blocks. But the layout parasitics of the analog section cannot be modeled by the digital behavioral model. As a result, the verification of system timing, voltage levels, and other parameters at the analog/digital interface is very difficult. Using the Verilog behavioral model for the analog section does not reflect the true functionality of the analog block. It is therefore risky to rely on this method for top-level functionality verification.

Figure 2: In a traditional verification flow, some design teams try to mimic the behavior of analog functions via a Verilog behavioral model.

Mixed-Signal Co-Simulation

Mixed analog and digital co-simulation is vital to ensuring correct functionality, as it verifies the interactions at both digital and analog interfaces. Such co-simulation can help identify effects like loading and level-shifting delays while validating other system-level functions. Typically, a mixed analog and digital co-simulation flow consists of a SPICE transistor-level simulator and a digital HDL (Verilog and/or VHDL) simulator. The biggest problem with this approach is that the total simulation throughput is always limited by the capacity and performance of the SPICE simulator.

SPICE simulators are the most accurate circuit-simulation tools. They’re used for the following: cell-level timing, the power and noise characterization of standard cell libraries, pure analog and memory-cell designs, and the verification of critical paths in digital designs in a static-timing-analysis flow. The high-accuracy goal of SPICE requires a highly accurate analog network solver, transistor device models, and other analysis modes. Those requirements lead to a solution that doesn’t effectively address the demands for the performance and capacity of full-chip mixed-signal verification. Typically, a very small section of the entire design can be simulated at the transistor level using SPICE. It usually requires a very long run time.

What can one do to improve capacity and speed? The answers are analog behavioral modeling and transistor-level simulation acceleration. For mixed-signal designers, behavioral-modeling languages like Verilog-AMS and Verilog-A have become very important tools for a top-down design methodology. They enable the early validation of the system without waiting for the individual design components to be completed. For top-level integration verification, however, the use of higher-level behavioral models can considerably improve the speed of simulation. While focusing on a few critical analog blocks and simulating them at the transistor level, designers can choose to model the rest of the analog sections in Verilog-A. Only the behavior of the analog circuits of interest is modeled, which results in much higher overall verification throughput.

This speed-up doesn’t come without a price, of course. The first cost is that behavioral modeling requires experts in both the circuit-application and modeling-language domains. Such people are difficult to find. Secondly, one must qualify and validate the Verilog-A model against the actual transistor-level designs. This qualification and validation requires answering several questions like the following:

• Is it fast enough?
• Is it accurate enough?
• Does it model device physical efforts?
• Does it work across the intended operating conditions?

The next difficulty to overcome is the continuing maintenance of the model library. No model is ever really “finished.� As soon as the transistor-level design changes, its Verilog-A model must be updated and re-qualified in order to account for new technology or circuit-operating conditions.

Transistor-Level Simulation Acceleration

A different approach is to rely on simulation acceleration. This class of tools is commonly known as “fast SPICE.� Instead of following the lead of SPICE simulators and solving a single large matrix, fast SPICE partitions the circuit into many smaller stages. Each stage will be solved as a single matrix, which results in speed-ups. Furthermore, the individual circuit that is partitioned can be simulated with a time-based or event-based algorithm. Each partition can therefore run at its own pace, effectively performing a very efficient multi-rate simulation.

Fast SPICE accepts SPICE and layout-parasitic netlists as inputs. It allows simulations to be “tuned� for throughput while relaxing its accuracy. If simulation accuracy will be acceptable within 3% to 5% of SPICE, for example, simulation speed can be improved up to 1000 times faster than SPICE with capacities over several million transistors. This solution is well suited for the simulation of phase-locked loops, charge pumps, analog-to-digital converters, large Flash and RAM memories, and large custom digital-logic blocks.

To address the top-level verification needs of today’s SoCs, designers need a sound verification methodology and a production-proven verification solution. To leverage the strengths of the simulators, a robust verification methodology for complex mixed-signal chips should rely on the careful partitioning of the verification tasks. The EDA verification solution must feature all of the techniques mentioned above.

Case Study: Digital And Analog Blocks

One such approach for the verification of complex mixed-signal and custom SoC designs is implemented in Synopsys’ Discovery AMS. This tool is based on HSPICE, NanoSim (fast SPICE), and VCS (Verilog/VHDL) digital simulators. It promises to enable the functional and timing verification of mixed-signal designs using the native design representations, such as RTL, gate level, Verilog-A, and transistor and post-layout parasitic RC netlists. It also uses the same regression testbenches that are used in the digital simulation environment (see Figure 3).

Figure 3: A comprehensive verification tool must be able to handle multilevel design abstractions while providing regression testbenches that can be used in digital simulations.

A recent customer case study demonstrated what could typically happen to any mixed-signal verification team. The large mixed-signal design contained a complex section in which digital RTL blocks and RF/analog blocks were part of the same closed-loop system. The designers wanted to verify the interactions between the blocks. They also wanted to measure key parameters, such as overall functionality, loop response time, and stability. Due to the size and complexity of the design, it was determined early on that an all-transistor-level verification approach wouldn’t be practical. Such an approach would require the cumbersome translation of Verilog testbenches into vectors. In addition, it would take over two days to simulate at the transistor level.

To save both time and effort on vector translation, the design team decided to run the tens of thousands of digital testbenches in the regression suite as they would in a pure digital verification environment. The analog blocks were instantiated directly into Verilog top circuits and simulated accurately with extracted post-layout parasitics. The entire regression run took less than 3 hrs. Several previously unseen errors were found using the mixed-signal verification approach. A sample list of these errors included the following:

• DC leakage path and floating gates
• DAC-signed digital-input signal that was reversed
• Clock-generation results that were incorrect due to a digital control trigger in the wrong active state
• Failure to power up under certain operating conditions due to initialization problem in the mixed analog and digital circuits

All of these problems were fixed without affecting the time to tape-out. Once it was received, the resulting chip easily passed all of the functionality tests. If those errors had gone undetected prior to tape-out, the result would have been mask re-spins. Even one re-spin would have cost the company lost time to market and significant financial loss.

As IC fabrication technology and design complexity continue to advance, so will the demand for the comprehensive top-level verification of analog and digital chips. At the same time, the cost of designing leading-edge SoCs and time-to-volume pressures will continue to rise. To ensure that designs work right the first time, a next-generation verification platform for mixed-signal SoC is required. This platform must enable engineers to meet SoC integration verification challenges by efficiently finding issues in system-level performance, A/D interface and driver-loading functionality, and the impact of multiple voltage domains and post-layout parasitics. The platform also must have the performance needed to handle full-chip simulation and the accuracy of foundry-certified transistor-device models. Deploying such a new verification solution will have a direct, positive impact on the SoC design’s overall cost of results.