Published on November 30th, -0001
As SystemVerilog establishes itself as the industry's preferred language for hardware design and verification, chip development teams are demanding well-defined methodologies that make the most of its capabilities. This isn't surprising since for verification alone, SystemVerilog adds hundreds of new language features that enable engineers to create powerful assertion-based, coverage-driven, constrained-random verification environments. When adopting SystemVerilog, where do you begin? A clear, concise, well-defined methodology provides the foundation and guidance chip development teams need to ensure verification success.
This trend towards defined methodologies isn't unique to design verification. For many years, software engineers have used well-documented process techniques to manage risk, deal with complexity and improve productivity. Properly conceived methodologies codify a set of best practice guidelines that unambiguously specify what should be done, or avoided, in order to efficiently produce error-free, interoperable and maintainable code. The clarity provided by a well-defined methodology enables engineers to focus on their unique design tasks, rather than addressing generic issues in setting up an environment. The industry as a whole also benefits from significant economies of scale that result from the widespread adoption of shared methodologies.
VMM Methodology Becomes De Facto Standard for SystemVerilog
The VMM methodology is defined in the best-selling book Verification Methodology Manual for SystemVerilog, released by Springer Publishing in September 2005, and has quickly established itself as the de facto standard for creating powerful, productive verification environments. Developed by experts from ARM and Synopsys, with contributions from reviewers at over 30 companies, the methodology defines industry best practices for adopting features of SystemVerilog to improve verification productivity.
The VMM methodology provides very clear guidance to engineers on how to set up a state-of-the-art verification environment in SystemVerilog. It enumerates hundreds of well-defined rules, guidelines and recommendations that make it possible for both local and geographically-dispersed teams to easily develop interoperable and reusable verification components. Other approaches to verification, which simply offer up a set of examples and leave the exact rules of the verification flow open to interpretation, may seem easy to implement at first but will not scale to deliver the full benefits of a well- defined methodology.
VMM Methodology Improves Verification Team Productivity
Hundreds of chip development teams around the world are successfully using the VMM methodology today, verifying everything from high-volume SoC and processors to complex FPGAs. One common theme in case studies published by these teams is that the VMM methodology improves productivity, saving weeks or even months off chip development time -- including the first project. As usage of the methodology spreads within and across these teams, internal collaboration, reuse and resource sharing become even easier, further increasing productivity.
There has been a substantial increase in the number of geographically-dispersed design teams, working on a single design across different time zones. A common, well-defined verification methodology enables them to share design data and verification IP easily, ensuring that remote working is no longer an obstacle to productivity within or across project teams. The VMM methodology provides the elements needed to develop a repeatable, standardized verification environment, which allows efficient communication between remote team members.
Methodologies that are based on in-house proprietary verification flows offer some consistency when deployed within an organization. However, this approach does not share the same economy-of-scale benefits possible with widely deployed methodology like the VMM, which include availability of services, commercially available verification IP, compliant tools and, of course, a skilled talent pool.
In fact, experience with the VMM methodology is now a sought-after, transferable job skill: an increasing number of employment advertisements for verification engineers specify VMM know-how as a prerequisite. As the global VMM talent pool grows, employers will find it easier to obtain VMM-ready engineers that can ramp up quickly after joining their verification teams. At the same time, a broader range of career options will become available to individuals familiar with the VMM methodology.
VMM Methodology Opens Opportunities for Innovation
The wide proliferation of the VMM methodology opens up new opportunities for chip development teams, service providers, and EDA tool vendors to innovate new ways to deliver even higher productivity. Just as SystemVerilog provided a platform that enabled emergence of an enormous variety of tools, methodologies, IP and services, the growing user base of the VMM methodology provides an economically viable foundation for the emergence of "VMM-aware" offerings. (See Figure 1)
The three components of Synopsys' recently-introduced next-generation VMM solution are examples of a new wave of methodology-aware, productivity-enhancing technologies.
VMM Planner improves verification predictability with systematic verification plan capture, tracking, and reporting. VMM Applications improve testbench development productivity with pre-built functions and tests for on-chip configuration registers, memory subsystems, data stream scoreboards, and more. VMM Automation increases verification execution and analysis productivity with methodology-aware tools, such as a VMM compliance checker, VMM-aware debug, and a VMM-SystemC transaction level interface.
The primary goal of the VMM methodology is to enable a fundamental improvement in verification productivity within projects, between project teams and across the industry as a whole. Its remarkable success, which has been achieved within a short time, is confirmation that it is has already met that milestone and is enabling design teams to move forward to even higher goals.