In astrology, conjunctions are portents that signal positive future directions.

I'm not completely convinced about astrology (we Ariens are well known skeptics); however, after attending some events and participating in various discussions at ESC San Jose recently, I predict that an alignment of tools, technologies, and standards is going to have a substantial bearing on how FPGA design is done in the future.

FPGAs enable quick design, and the star FGPA providers have substantial libraries of pre-designed Silicon IP and related tools that help customers to create designs rapidly. Rapid implementation technologies are only beneficial if matched with rapid design creation.

In traditional ASIC circles, there has long been recognition that IP reuse is the key designer productivity tool to economically exploit the opportunities offered by massive silicon capacity. Tried and tested IP, proven to work in existing designs, is likely to be much more reliable and robust than newly created IP being deployed for the first time. That recognition is feeding through to the FPGA world, where there is fantastic continuing progress in terms of performance and capacity.

But IP reuse can be challenging, because the benefits come from using the biggest and most complex IP modules, and these are the modules where designers have to spend a significant amount of time comprehending IP well enough to design it into their system.

The ability for designers to customize this IP gives the IP wider applicability (important for commercial IP companies and for users who want to use IP already proven through real-life deployment) but also significantly increases the verification challenges. To further complicate matters, the IP used in a design may come from many different sources – the optimum choice of IP module doesn't always come from the preferred silicon supplier.

Recognizing the problem of lack of standards in this area, a number of companies formed The SPIRIT Consortium to create an `electronic' databook format ("IP-XACT") that enables tools to share, understand, and automate the deployment of that complex and configurable IP into designs.

At ESC, Mentor and ARM ran a seminar featuring ARM's new FPGA processor, the Cortex-M1, along with design tools for that processor. The IP-XACT™ databook for this processor enabled me to use Platform Express™ (Mentor Graphics' IP-XACT design environment) to build substantial designs, incorporating the processor and a range of IP from different sources; to use generators (the modules that process the IP-XACT information into real design data) to create the required bus infrastructure for the AMBA bus; and to create the RTL version of the design.

I used a new generator to automatically synthesize the generated RTL using the Precision FPGA Synthesis tool. It took one click of the mouse to generate a detailed RTL design from the IP-XACT data, and it took a second mouse click to generate the bit stream file from the design, ready to program my FPGA.

This might seem mundane stuff, until I explain that I really don't know much about processor design in general and the Cortex-M1 processor in particular, and I am certainly no expert on creating the AMBA System and other busses that formed the backbone of my design.

I harnessed the specialist design knowledge built into the generators to automatically create the different elements of the design based on the IP that I selected. That same family of generators also allowed me to add verification IP to ensure the design was functioning correctly.

The interesting conjunction of which I spoke at the beginning of the article?

The Cortex-M1 processor uses a system bus and processor architecture that is common in ASIC design but not so frequently encountered in FPGAs. Because this IP was not developed by an FPGA vendor, individual FPGA design tools do not yet handle this IP and design infrastructure. However, the IP-XACT information enabled that IP to be used instantly within an IP-XACT design environment, without any requirement for next version tool updates.

The beneficiary of this conjunction of IP, tools, and FPGA silicon will undoubtedly be the design community. IP-XACT enables designers to access wider choice of quality IP from which to create their designs; generators to provide the specialist expertise to deploy that IP automatically; and links to the specialist tools from the FPGA vendors.

Designers can make the optimum FPGA choices guided by their chosen design content.

It doesn't take a prophet to predict that we are on the cusp of a new generation of modular design capabilities that unite the constellation of star tool, IP and FPGA vendors.

Share your star thoughts by contacting the editor at jkobylecky@extensionmedia.com and the Editorial Director at jblyler@extensionmedia.com.