Parallelism is changing the world. More specifically, parallelism is changing information technology and everything that depends on it. The driver has been for some time the hardware. In 2006, worldwide shipments of PC and x86 servers exceeded 239 million units. Cost effective "server farms" have been ubiquitous for many years. Since the advent of the first dual-core processor chip in 2001 (the IBM Power4), increasingly processors are becoming multi-core. The race for GigaHertz (GHz) has been largely overtaken by the race for multi-cores.

The second hardware trend driving parallelism is connectivity: On-chip CPUs can communicate over buses running at GHz. Gigabit Ethernet is a very cost-effective way of networking computers (there are faster solutions available) and the Internet provides access to virtually every computer in the world (albeit with some latency and bandwidth limitations).

What to do with all these CPUs? Among other things, write software that takes advantage of them. By itself this is obviously not new. For example, operating systems already take advantage of multi-core processors, even in consumer laptops; multi-threading has been practiced for quite some time. What is new is the scale: Applications which need resources can easily use hundreds or thousands of CPUs. Ideally, they should scale with the number of CPU's used: Increasing the number of CPUs increases the capacity and the speed of the application.

This brings us to design technology, which the trend towards parallelism is already transforming. In some cases, scaling is straightforward; for example, when running independent Verilog simulations or characterizing a standard cell library using SPICE. In both cases, each simulation is independent of the other simulations and all simulations can be run in parallel. Optical proximity correction (OPC) is more difficult to scale, but it runs routinely on hundreds of CPUs. It has to; otherwise computing a complex mask for an advanced technology node would take months or even years. OPC also happens to scale nicely.

But most design tools used today don't scale. The underlying algorithms were largely developed at a time where single processors were the only pervasive computing platform and the underlying theory dealt mainly with single processors. In many cases, parallelizing a given algorithm is hard and – even when it is possible – the resulting new algorithm doesn't scale beyond a few processors. Multi-threading the code for a design tool, for example, often allows execution of few threads in parallel, of the order of three to 10, but not much more.

What we need are truly scalable design tools. In essence, this means that by simply increasing the number of CPUs used by a tool ("throwing more hardware at a problem") you can run larger designs in less time. Scalability is often hard; may require invention; and typically has its limits, e.g. performance may scale up to a given number of processors for a given size of problem. Scalability, of course, depends on the problem being solved. Every tool or class of tools will require a different approach. An OPC approach – dividing the layout in possibly overlapping tiles and then running each of them on a different CPU – may work for other layout applications, but certainly not for circuit simulation. At the limit, every design tool will have to be rewritten.

Design technology that scales takes advantage of cost-effective compute resources and allows quicker turnaround of larger, more complex designs. Perhaps even more important, scalability enables new design methods and flows: Imagine simulating a circuit with millions of transistors (fully extracted, including power, ground and substrate coupling parasitics) with SPICE accuracy, in a matter of hours. Or imagine your most complex design "running overnight." Well executed, the scenario above may lead to a new golden era in electronic design automation, resulting in radically more productive design, more business and new growth.