Published on November 30th, -0001
What if you could produce hard-to-develop intellectual property (IP), the kind that has value and that requires continuous improvement, with minimal resource and predictable results? The networking and storage industries are ripe with opportunity for third-party IP providers who can keep up with the relentless drive for performance, features and cost reductions typical of those applications.
Hardware acceleration is increasingly the means to the radical improvements demanded by multi-gigabit data and storage networking. Supported by improvements in silicon geometries, hardware design teams are able to incorporate multiple, complex, high-order functions in chip-level end-to-end solutions. Often these teams turn to third-party IP providers for components that complement their own domain expertise, and wind up trying to integrate disparate pieces of IP that were never designed to work together.
Several issues confront IP designers -- third-party or otherwise -- who attempt to achieve the highest performance hardware offload for functions like compression/decompression, TCP/IP, packet filtering, IP Security (IPSec) encryption/decryption, Internet small computer system interface (iSCSI), etc. A primary challenge is that the most common hardware design and verification tools are too primitive, disjoint, time-consuming and resource-intensive to achieve predictable, high-quality results for large-scale complexity. At best, current design methods, which have serious practical limits for simulation testing, can result in market-delaying errors. At worst, they fail altogether.
Supplemental ESL (electronic systems level) methods that support higher levels of design abstraction have emerged to address the limits of traditional RTL (register transfer level) hardware design. Users testify that many of these fall short when it comes to development of complex multi-function systems. The industry debate over what "ESL" should be is ongoing. In general, contemporary ESL flows have particular areas of specialization; none is meant to completely replace RTL design entry at chip level; none attempts to address chip level verification. Constrained by available tools, third-party IP providers are similarly constrained in what they can effectively deliver. In the data and storage networking space, they are limited to bounded segments of protocols that are within reach of traditional RTL development flows.
Large domains of advanced networking protocols exist where timely and cost-effective hardware implementation could be achieved with an advanced silicon development methodology that incorporates an equally advanced ESL flow. Such a development methodology would establish a design framework, or "platform," for advanced protocols, with the objective of producing high-quality RTL.
An effective IP development platform allows for configurability of design components and flexible testing of the combinations. Hardware realization of any functional combination of the protocol components that make up the platform is possible. For high- level protocol IP cores, this translates to modularity with common interface and signals between components. Although the platform may show a processing path between modules A, B, and C, if an application does not require B, interface commonality is such that A can be joined to C, or some other sensible combination of processing can be used. For example, in a compression/encryption processing pipeline, although not particularly sensible, one could encrypt before compress by simply swapping the modules.
Within the development platform framework, subsystem components chosen for hardware coexist with several other related systems, and can be independently tested within the larger framework. In a facsimile of co-simulation, a particular component's RTL can run in a simulator while the remaining software moves the simulation forward. Combined with the commonality of interfaces, this sort of testing flexibility dramatically reduces the time and manpower required to deliver production quality, fully tested, synthesizable configurations and re-configurations of IP cores.
To be complete, the method of creating advanced data and storage networking IP cores requires an advanced ESL flow that can support unlimited design scale and that integrates with downstream synthesis flows (also not limited by scale). Both the ESL flow and the ESL language should be able to leverage the history of testing and practical hardening inherent in proven software embodiments as a means to accelerate project schedules and to improve quality. Within the networking/communications application space, this includes the large amount of open source code that exists, as well as support of standard ANSI C as an input design language. The maturity of such proven source can be immediately realized in the RTL output of the ESL flow, and would otherwise be difficult to duplicate in an original RTL design.
Going forward, designers of advanced networking and storage products must have access to tools that enable them to respond to market changes and to re-engineer or add to their designs while preserving their initial component investment. Hardware acceleration of complex storage and data networking algorithms is best achieved through an integrated hardware and software development environment facilitated by an advanced ESL flow. This represents a coalescence of many ESL concepts previously unrealized in the industry and provides a powerful platform on which to develop, design, verify -- and even market -- high-value, end-to-end data and storage networking IP cores.