Published on October 15th, 2007

Technology Book Review: Low Power Done Right

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Reviewed by Brian Bailey
Whether you're designing the next breakthrough in cell phones or the latest supercomputer, power is a major issue. So is getting rid of the heat that it creates. Perhaps we all have a social responsibility to ensure that the products that we create use the least amount of energy. In doing so, we could directly reduce our contribution to global warming. There are a number of ways to reduce power including the following: architecting solutions to provide the right amount of computation abilities at minimum power, architecting the software to efficiently use memory, and making sure that the implementation uses the latest techniques to minimize the amount of power that's wasted. If you're involved in the latter approach, "Low Power Methodology Manual For System-on-Chip Design" is a book for you. Synopsys and ARM have been working together for a number of years to bring together the best knowledge and experience from the leading on-chip processor vendor and a major EDA vendor. This book is written primarily by Michael Keating and David Flynn with contributions from Robert Aitken, Alan Gibbons, and Kaijian Shi. These individuals actually tried out a number of chip designs with the goal of providing readers with their combined experiences.

The book provides the theory, general practice, and a specific example associated with the techniques that they discuss. It starts by reviewing the current practice of clock gating. From there, it moves on to the new and more aggressive techniques of power gating and variable voltage and frequency. The book then discusses retention registers, power switching networks, and sleep transistors. An introduction to the Universal Power Format (UPF) is used to define some of the power domain information that is utilized by the tool flow.

The book's writing style is clear and easy to understand. Each section includes lists of recommended practices and some of the pitfalls that should be avoided when implementing these techniques. While I wouldn't describe it as a methodology manual, the book is a good description of some of the modern techniques that can be employed. In addition, the authors attempt to define how it should be incorporated into IP blocks so that they'll be usable when integrated into larger systems. Unfortunately, some of their recommendations aren't carried out in the examples because UPF and other preferred description means were developed after the authors started some of the example projects. These alternative implementation means may be useful, as UPF isn't yet universally adopted. Plus, the standards wars in this area continue to be fought.

If I have one negative comment about this book, it is the way that it treats verification. In many cases, this volume recommends against certain practices because they make the verification task more complex. But it only dedicates a couple of pages to actually talking about the methods that should be used for verification. I would've liked to see more suggestions about the impact that it would have on the various verification methodologies that are in use today-as well as the ways in which these can be extended to help with new and added complexity. For anyone wanting to reduce the power of his or her next chip, I thoroughly recommend giving this book a quick read before embarking on a project. That way, the right strategy can be developed. During implementation, the designer can always go back to the book for more help and guidance.

LOW POWER METHODOLOGY MANUAL FOR SYSTEM-ON-CHIP DESIGN
Series: Series on Integrated Circuits and Systems
Keating, M., Flynn, D., Aitken, R., Gibbons, A., Shi, K.
2007, XVI, 304 p., Hardcover
ISBN: 978-0-387-71818-7
Publisher page at: http://www.springer.com/west/home?SGWID=4-102-22-173747403-0
Brian Bailey is an independent consultant working with EDA companies in the areas of functional verification and the emerging electronic system level (ESL). Prior to that he was the chief technologist for functional verification at Mentor Graphics. He currently chairs two standards committees within Accellera, has published 3 books and has four patents to his name.

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