Published on October 31st, 2007

Layout Optimization for Yield -- A Case Study

At sub-wavelength geometries, many yield-loss mechanisms manifest themselves as layout issues. If these hot spots are not addressed as early as possible in the flow, they impact both time-to-market and revenue.
Renesas Technology Corporation is one of the top ten semiconductor suppliers in the world, delivering integrated circuits for a wide range of applications, including the fast growing PC/AV, digital consumer, and mobile markets. When Renesas engineers decided to move to 65 nm process technology, they knew they were up for a stiff challenge based on their experiences with layout-related yield issues at 90 nm.

At sub-wavelength geometries, many yield-loss mechanisms manifest themselves as layout issues. These are commonly referred to as "hot spots". If these hot spots are not addressed as early as possible in the flow, they lead to too many problems at the chip level and often defective silicon, as well. That impacts both time-to-market and revenue.

The Challenges
Renesas faced two major challenges:
  • Meet time to market requirements in a tight and unforgiving consumer-driven global semiconductor market.
  • Make manual repairs to layout hotspots, which was unfeasible for two reasons:
    1. Lack of time to address hot spots after tape-out.
    2. In a manual approach it is impractical to trade-off various yield-loss mechanisms, including the number of preferred rules involved in the process.
The Methodology
Based on their experience at the 90 nm technology node, the folks at Renesas understood that the number of layout hot spots will be much greater on a 65 nm design, with the majority occurring on the critical layers of a dense layout – diffusion, poly, contact and metal1. In other words, most of these problems occur on the layouts inside cells.

Thus, it was decided to first address the hot spots on cell "masters" in a library, thereby eliminating the need to fix the same hot spots on thousands of cell instances when they are instantiated on a full chip design later in the flow. This methodology reduces the number of times a layout fix is applied per design, as well as the time and effort spent on the same for each sub-sequent, sub-wavelength design.

Introducing Takumi Enhance
Takumi Enhance, an automated layout optimization tool from Takumi Technology Corporation, is designed to detect common layout-related yield-loss mechanisms (Table 1) in sub-wavelength designs and automatically fix the layout to eliminate the problems that have the highest impact on yield. When several thousand layout issues and a dozen or more preferred rules are involved, it is impossible to manually address all of the trade-offs, leaving automation as the only choice. Renesas decided that Takumi Enhance provided the automation they required.

Table 1
Table 1 Yield-loss mechanisms and ratings

When dealing with layout issues, it is important to understand that not all hot spots are fatal. Hence, a key characteristic of the required optimization solution is to identify the hot spots that have the most detrimental impact on yield and address them to maximize yield.

Using foundry- and process-specific information, Takumi Enhance detects and rates each hot spot by its potential impact to the yield in parts per billion (ppb). In addition, Takumi Enhance is designed to automatically trade-off the potential yield impact from the different layout issues and the preferred rules used in the system. The net outcome is a layout that is optimized for yield.

Customization to Ensure Yield-Loss coverage
In order to ensure adequate coverage of yield-loss mechanisms, Takumi Enhance is designed to allow users to program and add their own proprietary rating functions that cover unique failure mechanisms. Working closely with Takumi Technology, Renesas fine-tuned the built-in rating functions and also developed a custom rating function for addressing contrast-related yield-loss mechanism at sub-wavelength, thereby minimizing the risk of lower yield. This customization not only ensures quality of results, it also protects the users' investment in Takumi tools.

Conclusion : A Successful Deployment
After fine-tuning and developing a custom rating function and programming all design rules – including the preferred and recommended rules – Renesas deployed Takumi Enhance on their library layout over the period when the rules were being finalized (Figure 1).

Figure 1
Figure1. Takumi Enhance in the Renesas IC design flow

Takumi Enhance optimized the given layouts using its two-dimensional, fully automated layout manipulation technology, while trading-off various rules and yield-loss mechanisms based on the relative cost of each. This resulted in layouts that are optimized for yield – both parametric and catastrophic.

The library team achieved their objectives of:
  1. Saving time and effort: Closure on specific 65 nm libraries ended 65 percent ahead of schedule.
  2. Reducing risk and improving quality: Failure rates in PPB were significantly reduced by eliminating hot spots.
After this successful initial experience, Renesas has now deployed Takumi Enhance for production use.
Ravi Ravikumar is Director of Marketing at Takumi Technology Corporation. He has over 20 years of experience in the semiconductor and EDA industries. Prior to joining Takumi, Ravi served as Director of Marketing at LogicVision. He also held marketing, business development, and engineering positions at Synopsys, Cadence, and Fairchild. Ravi has a BE degree from the University of Madras and an MSEE from the Florida Institute of Technology.

Tech Videos

©2017 Extension Media. All Rights Reserved. PRIVACY POLICY | TERMS AND CONDITIONS