October 24, 2007 -- Semiconductor Manufacturing International Corp. (SMIC) and Cadence Design Systems, Inc. today announced that SMIC is offering a Common Power Format (CPF)-based 90-nm low-power digital reference flow and CPF-compliant libraries. SMIC also announced that it has joined the Power Forward Initiative (PFI).

The new flow uses intellectual property developed by SMIC and employs the Cadence Low-Power Solution. This flow is the result of a joint effort by Cadence and SMIC further strengthening their relationship and speeding up low-power designs for their mutual customers who face low-power design challenges.

The SMIC reference flow (3.2) is a complete CPF-enabled RTL-to-GDSII low-power flow aimed at efficient energy use for 90nm system-on-chip (SOC) designs. It incorporates SMIC 90-nm logic low leakage 1P9M 1.2/1.8/2.5-V generic process and commercial low-power library support. The flow features power awareness throughout all necessary design steps including logic synthesis, simulation, design for test, equivalence checking, silicon virtual prototyping, physical implementation, and complete signoff analysis.

"Joining the Power Forward Initiative shows our support for this industry-wide low-power effort and our pursuit of bringing advanced low-power solutions to our end users," said David Lin, Senior Director, Design Services Division at SMIC. "As advanced process nodes continue to shrink beyond 90 nanometers, two key issues have emerged: manufacturability and testability. The SMIC reference flow, based on the Si2 standard CPF, is a response to these issues. This gives us an efficient high-yield process that delivers the highest quality of silicon."