As IC system gate counts continue to grow, putting a complete system – including some memory blocks – on a CMOS IC has now become an everyday necessity. However, adding one particular memory technology – the non-volatile memory block – has historically been problematic for wafer fabs and IC designers, alike.

Today's wafer fabs encourage IC designers to take advantage of their lowest cost, highest volume mainstream CMOS processes, and to then add those less-used features (which typically include their own value-added intellectual property) as bolt-on process modules. The ideal non-volatile memory process module has four key objectives:

1. Add only a few more mask steps to the mainstream CMOS process.
   
2. Optimize use of the CMOS manufacturing flow and equipment set.
   
3. Have a negligible impact on the mainstream CMOS transistor models and corresponding IP blocks.
   
4. Scale effectively as CMOS process design rules shrink over time.

While non-volatile process modules based on a floating-gate (double poly) transistors have been used for over four decades, they do not meet these criteria, and this has prompted IC designers and wafer fabs to seek an alternative non-volatile memory process technology.

Two decades ago, the Silicon Oxide Nitride Oxide Silicon (SONOS) semiconductor manufacturing process was invented and successfully introduced into commercial IC manufacturing. SONOS uses a nitride charge trap structure ª– instead of floating-gate poly-silicon ª– to implement the non-volatile memory cells. This approach is particularly effective for fabs in adding non-volatile memory to system designs from an ease-of-manufacturing perspective, while also meeting the four criteria outlined above.

This article will review the SONOS technology with topics including:

1. SONOS advantages over floating-gate (FG) technology.
   
2. Typical SONOS characteristics.
   
3. Challenges faced by SONOS technology.

Advantages of SONOS over Floating-Gate
Over the past four decades, FG technology has been the major technology for non-volatile memory products such as NOR Flash, NAND Flash, EEPROM, etc. In recent years, the worldwide demand for Flash memories has exceeded that of the DRAM business. However, FG technology faces serious technical issues as it scales down beyond the 65 nm process technology node. While the FG-to-FG capacitive coupling between neighboring cells becomes increasingly significant [1], there is also a fundamental lower limit of the tunnel oxide thickness that occurs around 8 nm because of the data retention problem caused by Stress-Induced Leakage Current (SILC) [2,3].

Recently, Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) technology has been receiving increasing attention as an emerging alternative to replace the FG technology, due to its many advantages. Since silicon nitride-based non-volatile memory technology, Metal-Nitride-Oxide-Silicon (MNOS), was introduced for the first time in 1967, new variations of the trap-based non-volatile technology were evolved such as SNOS (Silicon-Nitride-Oxide-Silicon) and SONOS [4].

While a thick nitride layer of about 45 nm was used in MNOS and SNOS, SONOS was developed to reduce the nitride thickness by adding the blocking oxide between the nitride (storage layer) and the top electrode to confine the charges within the nitride layer. The quality and uniformity of the nitride film have been enormously improved, owing to the advancement in DRAM technology during the past two decades.



Figure 1. Comparison of floating-gate (FG) and SONOS transistor structures.

Figure1 illustrates the schematic device structures of FG and SONOS transistors. The technique of storing the charge is significantly different when compared between FG and SONOS. In the FG transistor, free electrons are stored in the conducting poly-silicon or the floating gate; by comparison, in the SONOS transistor, electrons or holes injected from substrate are trapped at trap centers in the insulating silicon-nitride layer, and are therefore not free carriers anymore. The trapped charge in SONOS offers a number of advantages over the free charge in FG devices.

In FG cells, a defect in the tunnel oxide, or in the inter-poly dielectric (IPD), results in a rapid discharge of stored free carriers, leading to an erratic memory storage bit. The oxide defect could be a pinhole or a stressed-induced defect (the source of SILC). FG non-volatile (NV) memory devices typically use CHE (channel hot electron) for program (write) operations and high-voltage FN (Fowler-Nordheim) tunneling for erase operations. Therefore, the program/erase cycles electrically stress the tunnel oxide, increasing the stress-induced leakage current. It is difficult to scale down the tunnel oxide below 80 nm because of data retention failure due to a catastrophic increase in SILC after continued program/erase cycling [2]. The tunnel oxide needs to be kept thick enough to meet the reliability requirement – typically 10-year data retention after 100,000 program/erase cycles. In addition, the thicker tunnel oxide requires higher program/erase voltages, and thus a higher-voltage charge-pump circuit, which in turn requires additional special process steps for high-voltage transistors, including an additional thick gate oxide, additional high-voltage wells, etc.

On the other hand, with SONOS, the data retention is not sensitive to a local oxide defect because charges are trapped and do not move freely. This feature allows the significant reduction of the tunnel oxide thickness, down to about 18Å and smaller. In turn, this thin tunnel oxide offers various advantages such as improved program and erase speed, reduced operating voltage, improved endurance reliability, improved total-dose radiation hardness, etc. A SONOS cell operates with direct tunneling or modified Fowler-Nordheim tunneling, which leads to a low-power operation, at the expense of a reduction in the programming speed. The thin tunnel oxide improves the speed significantly with a typical program time of less than 1 ms and an erase time of less than 5 ms for relatively low programming voltages of around 10V. The direct tunneling, or the modified FN tunneling, through a thin oxide does not cause any damage to the oxide, unlike FN tunneling through a thick tunnel oxide in the FG cell, which damages the oxide. This explains why the SONOS cell has a high immunity to program/erase endurance cycling.

As seen in Figure1, the stack height of the FG cell is almost twice that of the SONOS cell. The FG layer (the additional poly-silicon layer), is the primary reason for the larger stack height. There are two major limiting factors in the scaling of the FG thickness; the coupling ratio (CR) and the number of stored electrons. CR is the ratio of the CG capacitance to the FG capacitance and is indicative of the programming efficiency: the higher the number, the better. Leading-edge FG cells use the FG sidewalls to increase CR by simply increasing the total CG surface area. In addition, the total number of stored electrons is known to decrease with decreasing FG thickness, leading to less tolerance to electron loss. Therefore, the FG thickness is limited to approximately 80 nm.

In the SONOS cell, the charge-storing nitride layer is typically in the range of 6 nm to 10 nm, with the trapped charge evenly distributed throughout the layer. The charge beyond a certain distance from the tunnel oxide may not influence the threshold voltage, which determines the upper limit of the oxide thickness. The lower oxide thickness limit is determined from the requirement of the program-erase window size, as the total charge decreases with decreasing thickness.

By comparison, the IPD (Inter-Poly-Dielectric) layer in the FG cell is an ONO (oxide-nitride-oxide) stack which is formed by deposition. Its typical thickness ranges from about 15 nm to 20 nm (in equivalent oxide thickness). This should be kept twice as thick as the tunnel oxide to prevent electron injection into FG from CG during the erase cycle.

The top blocking oxide in the SONOS cell is a deposited oxide. Its thickness is in the range of 4 nm to 6 nm and needs to be thick enough to confine injected carriers in the nitride by blocking carriers from tunneling to the poly-silicon gate, and to suppress the electron back tunneling from the gate during the erase cycle. This electron back tunneling causes erase saturation, which limits the erase threshold voltage, and more importantly, degrades the endurance capabilities. This will be discussed in more detail later.

With respect to wafer fabrication processing, the SONOS cell process is much simpler than the FG cell. For example, in the case of embedded non-volatile memory, SONOS requires about three to four additional mask steps, in addition to the standard CMOS process, while FG requires about ten additional mask steps. Considering that one mask step requires an average of five process steps, the FG cell process requires approximately 50 more steps, which substantially increases the cycle time and the manufacturing cost of the devices. This greater number of process steps for the FG cell is mainly associated with one additional FG poly layer, the larger stack height, the high-voltage charge pump circuit, etc. Because of the larger stack height, the CG patterning and etch should be performed separately from that of the CMOS gate. The high-voltage charge pump circuit, due to the thick tunnel oxide, requires special high-voltage process steps, which include additional wells and additional high-voltage gate oxide. On the other hand, in the manufacture of SONOS cell, there is no additional poly layer required. In addition, the SONOS gate patterning and etch can be done simultaneously with the CMOS transistor gates, because the stack height is comparable with the CMOS transistors. The thin tunnel oxide does not require high program/erase voltages, and therefore the peripheral I/O transistors can be used for the charge pump circuit without any special process steps for additional wells and high-voltage gate oxide.

Typical SONOS Characteristics
Figure 2 shows typical program and erase characteristics curves for a SONOS transistor of W/L = 0.3 µæm / 0.2 µm with a SONOS structure of 18Å tunnel oxide, 90Å oxynitride, and 40Å blocking oxide with an N+poly gate (pulse voltages are +11V for program and –10V for erase; erase saturation occurs from about 30 ms). The transistor was fabricated as part of a 4 Mb nvSRAM [5] using a 0.13 µm CMOS process, with additional ONO process steps.



Figure 2. Typical program and erase characteristic curves for a SONOS transistor.

It is noted that the erase threshold voltage saturates for long pulse widths. This erase saturation is primarily due to the erase pulse height (Figure 3). As the pulse amplitude increases, the device is erased quicker and saturates faster, and the saturation threshold voltage increases. The erase saturation has two major negative effects: (1) a narrower window due to increased erase threshold voltage, and (2) more importantly, endurance degradation.



Figure 3. Erase curves for different voltages (–10V, –11V, and –11V). Saturation Vte increases with increasing erase voltage.

During the erase cycle, holes are injected into the nitride from the substrate by band-to-band direct tunneling. Injected holes are mostly trapped or recombined with trapped electrons. Subsequently, injected holes pile up at the blocking oxide interface, increasing the electric field across the blocking oxide, thus causing the electron FN tunneling into the nitride from the gate. Erase saturation occurs when the hole tunneling from the substrate dynamically balances with the electron back-tunneling from the poly gate [6]. Some electrons tunneling to the substrate damage the silicon/tunnel-oxide interface, generating interface states and degrading endurance.

The erase saturation can be improved by increasing the blocking oxide, or decreasing the erase voltage, with a cost of either an increased erase time or a decreased program/erase window due to increased erase threshold voltage. For a given ONO process, a trade-off needs to be made between the erase time and the program/erase window. By using a P+ poly gate instead of an N+poly gate, we can suppress the electron back-tunneling, and thus improve the erase saturation without any negative effect on the erase speed [6]. To ensure endurance reliability, the erase pulse condition should be different than that of erase saturation. Figure 4 shows very robust endurance characteristics, even after 1M cycles for an erase pulse of –10V/3ms with a program pulse of 11V/1ms.



Figure 4. Typical endurance characteristics for program pulses of 11V/1ms and erase pulses of –10V/3ms.

As described earlier, the data retention in SONOS is not sensitive to a local oxide defect, because charges are trapped and do not move freely. This characteristic allows for a reduction in the tunnel oxide thickness significantly (down to about 18Å). Therefore, the charge loss in SONOS with a thin-tunnel oxide is mainly governed by the thermal activation of trapped charge. In other words, once a trapped charge becomes a free carrier, it tunnels back to the substrate immediately through the thin tunnel oxide, and the trap energy level is important in this process. If the electron trap center is deeper than the conduction band edge, then a higher thermal activation energy is required for the trapped electron to be thermally activated to the conduction band and to become a free electron.



Figure 5. Typical retention decay curves for various temperatures.

Figure 5 shows typical retention decay curves for various temperatures after 200K cycling with the same pulse conditions as for the endurance test. The current state-of-the-art SONOS process demonstrates excellent data retention, even after 200K endurance cycles, as characterized by an EOL (End-Of-Life) window of > 0.5V after 10 years (8.5 in logarithm of seconds) at 85°C, which is all that is required to distinguish between a logic "1" and logic "0" in an non-volatile memory element. It is noted that the decay of the program state (electron trap) is faster than that of the erase state (hole trap), as expected from the different tunneling probability between electrons and holes. Hence, the data retention is governed more by the program-cycle decay than the erase-cycle decay.

Challenges Faced by SONOS Technology
Although SONOS technology offers many advantages over FG technology, there are some areas that have room for improvement. Among these are the program/erase window size and the variation of the program and erase threshold voltages, which are the two most important considerations, especially for multi-level cell (MLC) applications, where the threshold difference between the erase and program state become even more important than in single level cell (SLC) applications.

The window size is determined by the total trap density in the nitride. The typical trap density in a nitride film is known to be in the range of 1E18 to 1E19 cm^3 [7, 8]. Bandgap engineering, by varying chemical compositions among silicon, nitrogen and oxygen, was demonstrated as a promising method to improve the silicon nitride properties [9]. The nitride using a silicon-rich bottom region near the tunnel oxide was found to improve the size of the window. Continued improvements can be made in this area for further optimization by controlling the trap level (creating deeper traps), as well as the density. The bandgap engineering can also improve the reliability both in endurance and data retention.

The variation in the program and erase threshold voltages is known to come mainly from a thickness variation of the top blocking oxide. This oxide is typically a high-temperature deposited oxide (HTO), which is easily etched during process steps, even after densification. The block oxide formed by high-density plasma (HDP) oxidation of the nitride layer was introduced to improve the thickness uniformity, as well as the oxide quality [10].

Recently, a novel nitride-based TANOS (TaN/Al₂O₃/Nitride/Silicon) cell technology was introduced [11]. The high-K dielectric blocking layer, combined with a higher work-function metal gate, allows a thicker tunnel oxide to be produced, without losing the program/erase speed, yet also improving the data retention. This structure also improves the erase saturation, and thus the endurance. The same group that developed the TANOS technology presented a TANOS-based multi-level 4 Gb NAND Flash using the same circuit design as the multi-level FG-cell NAND Flash memory at the 63 nm process node [12].

The SONOS-based two-bit cell (the so called NROM or Mirror-Bit) was introduced, whereby the charge storage is localized at drain or source side [13]. The cell operation requires channel hot-electron injection (CHE) for program operations and channel hot-hole injection (CHH) for erase operations with a thicker tunnel oxide of around 4 nm. This offers two major advantages. First, of course, is the increase of the effective density by providing two-bits per cell, and second is the faster speed in program and erase operations as a result of the hot-carrier injection. An obvious disadvantage, however, is the higher operating power due to higher program and erase currents. In addition, this cell has three distinctive issues involving endurance, retention and technology scaling. The endurance issue comes from the increased net charge remaining in the nitride after endurance cycling due to mismatching of electron and hole packet locations. The charge retention after cycling degrades significantly due to trap generation by the hot-hole injection in the tunnel oxide, and thus the increase in the SILC. The electron spread-out in the nitride makes the electron charge separation between the source and drain packets difficult as the technology scales down. This scaling limit may partially be compensated by the benefit of its two-bit capability.

The gate read disturbance is recognized as an issue in the SONOS cell for a non-zero read gate bias [14]. The charge loss of the program state is accelerated by a negative gate bias, while that of the erase state is accelerated by a positive gate bias. Therefore, the SONOS transistor should be designed such that the program/erase window center is around 0V and the read gate bias is set at 0V, minimizing the gate disturbance.

Summary
We reviewed the SONOS process technology focusing on its advantages over the floating gate technology, typical state-of-the-art SONOS nonvolatile characteristics, and challenges for further improvements.

Compared with the floating gate cell – which stores free charge in the conducting poly-silicon layer – the SONOS cell with charge trapping in the insulating nitride layer allows the significant reduction of the tunnel oxide thickness. The thin tunnel oxide offers a number of advantages, such as improved program and erase speeds, reduced program/erase voltage, improved endurance reliability, improved radiation hardness, etc.

The use of the thin nitride as a storage layer, instead of using the thick floating gate polysilicon, leads to a comparable stack height with the standard CMOS transistors and simplifies the fabrication process and extends the scaling limit. The smaller stack height along with the reduced operating voltage significantly reduces the number of process steps required for adding the embedded NV memory in addition to the standard CMOS process, resulting in a significant reduction in the cycle time and the manufacturing cost.

We demonstrated our recent data that shows excellent SONOS nonvolatile characteristics. The endurance up to 1M cycles did not show any significant degradation in the program and erase threshold voltage, so long as the erase pulse condition is chosen away from the erase saturation pulse condition. The data retention at 85°C after 200K cycles meets the requirement of a 10-year EOL window > 0.5V.

We also reviewed recent progress of some challenge areas for further improvement of the SONOS technology. The two most important areas that need to be improved upon for multi-level cell (MLC) applications are to increase the program/erase window size and to reduce the variation of the SONOS program/erase characteristics. Recent bandgap engineering of the charge-trap nitride layer appears to be very promising to increase the program/erase window, as well as to improve the data retention by increasing the trap daensity, and also by making the trap energy level deeper in the bandgap, respectively. The top oxide thickness variation, which is primarily responsible for the variation of the SONOS characteristics, was demonstrated to be improved by using the high-density plasma oxidation of the nitride layer, or by the high-density plasma nitridation of a thick oxide which can form the three layers (oxide-nitride-oxide) simultaneously. It was demonstrated that the use of a high-K dielectric layer like Al₂O₃ for the blocking layer with a metal gate like TaN can further improve the NV characteristics by relaxing the vertical thickness scaling, improving the erase saturation, etc.

When all optimizations are in place, we expect that the SONOS technology may be able to expand the nonvolatile memory technology node by two or more generations beyond floating gate technology.

Acknowledgements
The author would like to thank Brad Hartman, Grant Hulse, and David Still for their support and encouragement.

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