Many factors contribute to the cost of bringing a new IC product to market. Every year, advances in foundry processes and EDA tools and techniques allow companies to create larger and more complex chips. But there is an economic downside to these technology improvements. Typically, the total cost of a new IC design is measured in the millions of dollars. This article will help shed light on the total cost of developing a new IC by focusing on the ASIC development flow.
The basic ASIC-based product-realization flow starts with a Specification Phase. Here, the basic product specifications are determined based on market or technology needs. Next, tradeoff studies are done to determine make-versus-buy decisions for each major design block.
After the specifications have been determined, the Engineering Phase can begin. During this state, new or unique design parts are developed and major design blocks are verified. All of the blocks are integrated. The resulting integration of blocks is then verified. The output from these previous steps is verified RTL code and perhaps some GDSII for the purchased blocks. Synthesis, placement, and routing can now commence along with timing analysis.
The subsequent Manufacturing Phase results in the generation of a mask and the actual manufacturing of the chip. Packaging and test activities also are conducted during this phase. The final task is to assemble the chips into their appropriate products or packaging for re-sale.
Today's large ASICs are made possible by design re-use. Sometimes, the term �re-use᾿ connotes the re-use of blocks from previous designs. Other times, it means purchasing blocks from an intellectual-property (IP) provider. Purchasing IP usually implies several costs: the cost of purchasing the IP, the per-chip/per-design royalties, and the often-overlooked cost of verifying the IP in the chip or application. One panel at this year's DAC mentioned a customer paying 10 times the cost of the IP to verify it.
Let's think outside the die for a moment. What other factors contribute to chip cost?
Each step in the process can imply costs in more than one way. For example, a simple concept like power or pin count can affect final product cost in several ways. Mounting a bare die on a board is the most inexpensive route. But bonding out too many pins directly can affect the final yield. After all, direct-bonding machines tend to not work well with high pin counts and fine pitches on the pads. A direct-bonded die may not be able to cool if it consumes too much power. In addition, the packaging costs go up as a continuum from bare die through plastic packages to ceramic packages. The ceramic packages can handle the most pins and power. Too much power dissipation also can translate into a requirement for a heatsink/fan, which will increase the total system cost.
At some level of abstraction, people with industry experience may be able to wave their arms and guess at a cost within a few million on the development and a few dollars on the final chip cost. These rules of thumb, which have been learned by experience on previous chips, can be good enough to start an initial business plan. Yet detailed estimation also may be required.
Looking at a growing laundry list of items that contribute to cost so far, it's possible to tally:
Inside the die:
• One-time or fixed charges
• IP-procurement costs
• Engineering-design costs
• Verification costs
• Mask charges
• Other NREs
• Per-chip costs
• IP royalties
• Die cost
• Bad-die cost (defects)
Outside the die:
• One-time or fixed charges
• EDA-tool licensing
• Generation and setup of test programs
• Load boards, probe cards, and other test NREs
• Generation of documentation
• Market timing costs
• Per-chip costs
• Package cost
• Assembly cost
• Test cost
Now go back to the premise of purchasing most of the blocks for the ASIC. Where do designers go to find detailed information about what blocks they can purchase? Typically, engineers can look at their favorite IP portal(s) on the Internet. Next, they need to find out the area and power information for each block and start plugging numbers into a spreadsheet. Using this method, trading off one vendor's block against another requires additional effort. Of course, the designer will end up negotiating the pricing with each vendor based on that vendor's licensing and royalty model.
Design-service firms like The ASIC Group can help designers estimate and execute the engineering phase based on the chip's size and complexity. Good decisions made during the engineering and specification phases can affect cost dramatically. Was the chip designed to be easy to verify? Was it designed to be easy to test? What precautions were engineered in order to minimize risk and reduce the number of spins?
The Spin Cycle
In the late 1990s, the goal was to first pass correct silicon with no spins. This goal was accomplished frequently. Today's chips are much more complex. As a result, the risk of a spin is increased. The cost of a spin may be minimal with only a metal-layer change. Or it may be a full redesign of some areas, thereby recurring the costs of several steps. Some companies plan on a certain number of spins in their overall costs and schedule.
It's essential to realize that the cost of a spin itself contains many factors, such as the engineering and verification of the changes. In addition, the cost of manufacturing the changes will vary based on if it is a full re-spin or just a metal mask change. The packaging and testing of new parts also factor into the cost of a spin. Additional factors to consider include the market timing costs when a product is delayed.
Verification is one way to reduce the number of spins. But the perpetual question of when verification should be done remains one of the world's great unanswered questions. Today, there are many more choices for verification than just simulation. Verification is accomplished with a whole suite of tools and teams of people. The cost and time of additional verification tools, people, and time needs to be traded off against the cost of additional spins.
The common processes that are in use today vary from large feature sizes for analog down to the common range of 350-nm to 90-nm for digital processes. The process may be dictated by a desire for power or speed. Or it may be restricted by some of the blocks, which require certain processes like embedded flash or analog components. Because process affects performance and power, all of the factors are interrelated.
When making a decision about processes, there are many variants to consider. A designer may be able to start out with a broad-brush approach and narrow down the basic feature size to a few potential processes. But the variations will continue with each foundry and across the variants of low voltage, high speed, low leakage, etc. Perhaps an engineer needs to trade off the lower NREs and mask costs of a 180-nm or 130-nm high-speed versus a 90-nm low-power library. Such a tradeoff would be appropriate if the design was in the performance overlap of the technologies.
With so many factors affecting cost, where can engineers get help? One method is to contact multiple service firms and ask them to help with the estimates. Then, just take all of the estimates and work them against each other in a set of spreadsheets. Another method is to use a chip-development estimation tool like Giga Scale IC's InCyte (www.ChipEstimate.com). At The ASIC Group, I have used previous versions of this tool to estimate area, power, and cost for various projects. The latest version of InCyte allows for more detailed economic analysis. It accounts for more of the factors that have been listed in this article.
Say a hypothetical customer wants to create the J-pod. This hypothetical media player will have an internal laptop hard drive to store movies, photos, and music. To load and store content, it will have an SD card slot. The media player will have USB-on-the-go for use as an external hard drive for loading and storing media or to master the USB to download from other USB disks or DVD players. Of course, it will have a color liquid-crystal display (LCD) for the user interface or watching videos. The magic sauce to be added is 100 kgates of media compression/decompression, decryption logic, and software. It is estimated that 150 millions of instructions per second (MIPS) of peak processing power will be needed. The company's marketing department would like the product to hit the market with a $99.00 street price.
A quick look around may find some ASSP parts with some of the interfaces. But additional circuitry will be needed for the custom logic. A decision is made to look for all of the IP and come up with some estimates. The requirements imply that other IP is needed, such as timers and DMA and SDRAM controllers. All of these parts will be added into the estimate. Additionally, some internal memory will be required for buffers and caches. Memory area is a significant factor in the overall chip area. To get the size estimates, the memory generators need to be run.
Doing the analysis for one technology and one set of IP sections by hand is a huge task. The task of doing the analysis also can be huge when one considers wanting to trade off foundries, libraries, technologies, and different IP vendors for common blocks. Other complications, such as which IP blocks and memories are available in each technology, can make working out the estimates a daunting task.
With a proven chip-estimation tool, that task becomes much easier. With these tools, the engineer can pick an initial technology and define clocks. The designer can then select the amount of random logic that he or she expects to add in each clock domain and define the IO pins. Next, the engineer will figure out a rough shopping list of the blocks that are needed. Using the built-in browser or IP search engine, he or she can look at available blocks that could suit the project. Once there is a basis for the estimate, it's time to begin adding in the list of memory types and sizes. Tools like InCyte use the memory-generator information in its estimates so that memory generators don't need to be installed or run manually.
Once this step is completed, the initial estimate should be saved as a project. Start making modifications like changing IP blocks, vendors, or technologies. As the technologies are changed, use a technology mapper to cross-map to equivalent blocks. Each project that is saved out can then be easily compared in the tool. The reports that are generated allow designers to look at the expected die price using either industry-average wafer cost and yield numbers or plugging in their own.
Of course, the raw cost of the die is a small portion of the overall chip project and a small step in the overall life cycle (see Figure 1). As mentioned earlier, the power and pin count drive the package and the package price. These prices are usually much greater than the raw die cost.
Figure 1. Estimating die usage is just one capability of a chip-estimation tool.
Going back to our J-pod example, 150 MIPS of processing power are needed. Many processors could be used. If we originally picked an ARM10 just to have more than enough processing power for the future, we might find that the power consumption forces us into a thermally enhanced or ceramic package. We may then reconsider, as a new part of the tool advises the user on package choices based on the pin and power estimates from the engineering estimate. Were the MIPS estimates from the software team accurate? Could we scale down to a smaller, lower-power processor like an ARM7? Would we be better off with an ARC or Tensilica processor with special instructions to take care of the processing bottlenecks?
Being able to make these tradeoffs early in the planning cycle can have a huge effect on both the final chip cost and the direction of the engineering effort (see Figure 2). Waiting until the design is mostly done to look at power and packages may result in a non-profitable chip or the need for a redesign to cut costs. The redesign effort may result in a missed market opportunity. As other aspects of the cost are narrowed down, such as non-recurring-engineering (NRE) IP costs and royalties, they also can be plugged into the total cost equation.
Figure 2. InCyte provides an economic analysis engine to help make tradeoffs between variables like power and packaging.
A number of common designs exist for test techniques that can be employed during the engineering phase of the project. Test techniques are interrelated to the primary design issue in terms of the final cost of the project. For example, a technique like �scan᾿ is common. It adds power and area, which both contribute to cost. Yet �scan᾿ also makes the chip easier to test and can reduce tester time, which contributes to cost. The impact of tester time may be a significant factor in a high-volume consumer chip. Up-front engineering effort in designing the chip to be testable may therefore be a viable economic tradeoff. The same statement can be applied to later effort in reducing the test-set size (see Figure 3).
Figure 3. Estimating test-related costs like scan can reveal cost increases from increased power and area. They also can pinpoint the cost savings derived from reduced test times.
This article touched on some of the many factors that contribute to the overall cost of an ASIC design. Will it be a profitable product? Based on costs and projected volume, is the design better off in an ASSP, FPGA, or structured ASIC? All of these questions must be answered before going too far down the economic road of your next chip design. As you start to work out the high-level specifications for your next chip, consider all of the areas that we touched upon in this article (see Figure 4). You might even add some costs that are specific to your company, such as internal charges or the cost of maintaining stock items. You can do all of the work manually or use automated cost-estimation tools to run your estimate. In the end, you may be able to plug in life-cycle predictions and calculate your ROI.
Figure 4. The data from the estimates is rolled up into a budgetary estimate.
Chip estimation tools like InCyte base their analysis on either industry average or specific foundry and IP vendor data. Say you decide to work with a full-service ASIC foundry or even a fabless semiconductor house. You can take the detailed estimate that you created as a �Request for Quote᾿ to any ASIC providers with which you wish to work. Through their volume purchasing power, some of the foundries may be able to get you better pricing on die, IP NREs, or royalties as well as other costs like layout services, masks, packaging, and test.
At www.ChipEstimate.com, you can download a free version of InCyte and experiment with some of the simple process tradeoffs in a generic sense. Purchasing an InCyte upgrade will enable more accurate chip estimation targeted at specific foundries and IP vendors process and technology data as well as allow comprehensive economic analysis and packaged recommendations. Note that many of the features and capabilities that were discussed in this article are part of the upgrade subscription. ◆
James M. Lee is President of The ASIC Group Inc., a Silicon Valley-based design-services firm. He also is the author of Verilog Quickstart, which is now in its third edition.
Are you up-to-date on important SoC and IP design trends, analysis and market forecasts?
Chip Design now offers customized market research services.
For more information contact Karen Popp at +1 415-305-5557
San Jose, CA September 30, 2014
Santa Clara, CA Oct 1-3, 2014
Munich, Germany October 14-15, 2014
Congress Center Düsseldorf October 20-21 2014
Seattle, Washington October 21-23, 2014
Irvine, CA October 22-23, 2014
Scottsdale, AZ November 5-7, 2014