Published on November 11th, 2005
Designing high-performance analog and mixed-signal chips has never been easy. In fact, analog design has often been regarded as a black art. With the need for ever-higher frequencies and data rates along with ever-lower consumption, however, analog design is becoming increasingly important for wireless equipment. Equipment makers are demanding significant performance improvements for each handset generation or roughly every six months. In addition, the need for more functions in terminals is driving up power consumption. This need can help to optimize the design of the individual analog and mixed-signal devices and architectures in order to reduce power consumption. But the reality is that the time taken to develop new, increasingly complex wireless chips is increasing.
Some significant challenges are spawned by these trends. For example, higher power densities have to be supported as the chips get smaller. The noise margins are ever decreasing to provide higher performance. Such higher performance will reduce duty-cycle times, which will in turn lessen the current drain. Reducing the length of signal lines, the coupling between lines, and the noise in the system (so that it can run at a lower voltage) all reduce the power consumption. But this reduction is hard to achieve with many of today's design tools.
These designs also must match the manufacturing process in order to hit the sweet spot and provide the best possible yield in the shortest possible time. Some analog chip designers will trade off many revisions of a mask set, which costs millions of dollars, just to get a one-percentage-point increase in yield.
It's also important to make the chip as small as possible. Size hasn't been a critical factor in many analog designs. Traditionally, the space on the die is used to provide more isolation. But mobile phones are small, high-volume products. Shaving just a few square millimeters from the die size can cut a few cents from the cost and lead to savings of millions of dollars.
A lack of appropriate design tools has meant that layouts are still often done by hand. This manual approach limits the designers' productivity while extending the time to market. If there are problems with the layout, costly re-spins are needed. Such re-spins hit the profitability of the company and delay the introduction of new products. For this reason, good analog chip designers are worth their weight in gold.
The emphasis is certainly on time to market and--maybe more importantly--on time to yield with the lowest possible area. As a result, the designer's attention is fixed on getting the design right as quickly as possible. Most analog and mixed-signal design tools focus on the capture and simulation of the design. Yet routing is key to getting custom chips out at the right time and ready for manufacturing.
Many of the yield issues in manufacturing result from problems with signal integrity, matched and shielded differential signals, resistance- and capacitance-constrained paths, and current densities. Given the right technology, all of these elements can be optimized and improved through the routing process.
In many chip-design areas, the established view is that the technology for routing metal between the elements in a design is mature. There is therefore little room for innovation. But analog designers--particularly in the wireless arena--haven't seen the benefits of design automation. The blame partially falls on traditional grid-based routing algorithms, which are used by most routing tools. These algorithms don't match well with the requirements of analog and mixed-signal designers.
The grid-based algorithms take a complete design and break it up into a grid of small squares in a database. They block out areas of the grid where components prevent wires from being routed. Wires are then routed on an XY grid to link up components in the design. The number of squares in the grid is used to determine the minimum path for the routing.
This technique is hugely memory intensive. As a result, the majority of the design data is dropped from the routing database. Such data includes what the components are and how the wires could interact. Yet this process is still slow. To improve the speed of these grid-based routers and reduce the memory requirements, a technique called global routing is used. This method first routes on a series of large grid squares. To produce a routed design, a fine-grid approach is then used in each of the larger grid squares.
These squares are too large to allow the router to consider the detailed positioning of interconnects. They are used to solve global problems, such as congestion, rather than problems with individual nets. Once the global routing is complete, the fine-grid approach is used on each of the larger grids to produce the routed design.
The problems of getting a design to market with a small die size and a good yield are a direct result of the problems of grid routing. The inherent XY routing of the grid doesn't lend itself well to the components that are at the heart of analog designs. Such components include phase-locked loops (PLLs), voltage-controlled oscillators (VCOs), mixers, and low-noise amplifiers (LNAs).
Many design tools are adding signal-integrity and parasitics analysis. Without the component and wire information, however, grid routing cannot add these types of analysis. Nor is the grid approach the most efficient use of area. Because of these two factors, more design margin--both in area and signal integrity--has to be left. The result is a die that's larger than necessary.
A problem also exists with changes. Each time there is a change, the design has to be re-routed completely. It doesn't matter if the change is from an engineering change order, simulation, or a timing- or power-analysis tool. It takes time and often many iterations for the design to converge on a solution that fits the specification of the manufacturing process. A lot of time also is taken up just making the design fit the process, rather than optimizing it for the process' sweet spot in order to get the best yields. To speed up the design process and enhance the yield of the end devices, analog designers have been moving to a different algorithm: shape-based routing.
As designs get faster, wires get smaller and closer together. Signal-integrity problems like crosstalk then become critical. Often, such problems prevent a design from operating. Shape-based routing allows wires to be routed closer together and more accurately. It also takes into account critical elements, such as RC coupling and transmission-line effects, while the design is routing. This capability isn't possible with existing technology.
Shape-based routing doesn't use a grid. Instead, it creates a �flood᾿ in one direction until it reaches an obstruction (see Figure 1). It then finds an unobstructed edge in the direction of the target. It floods in that direction until it reaches another obstruction. This process repeats until it reaches the target.
Figure 1. A shape-based routing algorithm is used to determine the route between two points by flooding. The routing uses the full design data, allowing interactive signal analysis.
Each edge is assessed or �costed᾿ for the distance it takes as well as factors like resistance, capacitance, crosstalk, and current density. All of these factors are vital for an analog layout. The costs are kept throughout the run, as one route may end up in a dead end or high-cost route. Another, further-back option may result in a lower-cost route overall. This technique is coupled with �rip up and re-try,᾿ in which the cost of an error also is included in the calculation.
A key advantage of this approach is that each net is routed with the full knowledge of its surroundings. It also is routed with access to all of the data in the design database for the net, all of the components in the net, and all of the adjacent nets and components. As a result, real data like wire widths, characteristics of nets, and timing information can be used to accurately predict the effect of the parasitics in the design. It doesn't matter if they are aggressors or victims in crosstalk.
A wide range of data can therefore be used while the design is being routed. To get the most efficient routing the first time around, a route can be compared against the design-rule-checking and signal-integrity analysis tools. This capability can dramatically reduce the design time compared to going through the many iterative cycles of routing and post-processing. Such iterative cycles are necessary with the grid-based approach.
The focus on a detailed solution for each individual net is ideal for analog chips. Those chips tend to be significantly smaller than the million-gate digital devices. After all, the process can be interactive and iterative.
If something is obviously wrong, the designer can stop the automatic routing and make an adjustment. He or she can even route a particular section by hand and then continue with the auto-routing. This option just isn't possible with the global grid-based routing. It couples the expertise of the analog designer with the productivity gains of a design-automation tool. The designer can therefore create better designs in a shorter time, hitting those vital time-to-market and time-to-yield targets.
Compared to the digital arena, it has been much harder to bring design automation into the analog world of irregular shapes and constantly varying voltages. But shape-based routing succeeds in delivering productivity gains without de-skilling the analog and mixed-signal designer.
Another advantage of storing the detailed connectivity information with the truly representative component data is that �push-aside᾿ techniques can be used. The routing algorithm can then identify areas where it may be able to pass by moving an existing wire out of the way. This capability isn't possible with a global grid algorithm. Instead of having to run yet another batch job, the push-aside techniques result in shorter wires and higher routing efficiency during the routing process.
The point is not to squeeze as many wires together as possible, however. Having the analysis tools and net information available during the routing is a key advantage. The analysis of the wires can determine whether the tracks can be squeezed together safely or whether they need separation to maintain the timing and noise requirements.
The same thinking applies to spreading the tracks or making them wider to reduce the resistance and RC delays. More margin can meet the timing requirements. At the same time, that margin is allowed to be applied throughout the routing process, rather than having to go through the process again with batch-based analysis.
A key advantage exists over grid-based algorithms: The spreading of the tracks often pushes the tracks over the boundary of the grid and into another square. With grid-based routing, this adds space while making the routing process less efficient. As a result, the end chip is more costly.
The ability to route at a 45-degree angle--called mitred routing--also is important to analog and mixed-signal designs. Recently, it also has become possible in some grid-based routers. Because shape-based routing isn't confined to the grid, this is just an option in the tool. Any angle is possible. This aspect helps with the layout of the components and new packaging techniques, such as flip chip, that help to reduce the die area.
With the batch-based approach dictated by grid routing, the parasitics have to be analyzed after the routing has taken place. The routing data must be added back into the main design database. The design is then re-routed on the basis of the analysis results. Next, another analysis is done to ensure that the routing layout is viable while identifying new problem areas in the design. If the designer is lucky, this task can be done in small areas without significantly altering the overall design.
Many signal-integrity problems occur with lines running across the chip, however. Optimizing these lines often involves re-routing the whole design. In this way, the design converges on a solution after many iterations until the final tradeoffs of area and performance are balanced. In such a scheme, a fast algorithm is critical to reducing the overall time taken for routing.
This method differs from the approach that's made possible by shape-based routing. All of the design data is available during the routing process. As a result, the parasitics are part of the �cost᾿ analysis. Because they're directly tied into the design-rule-checking tools, the routed path will meet the design requirements from the first attempt. Even when tracks are pushed aside to make room for new tracks, that change is incorporated into the routing process. New decisions in the auto-router take this into account, as it is using the underlying design database.
Post-layout analysis tools and iterations are still needed. But they're used to check variations that can be introduced while identifying areas that could benefit from tighter or looser design rules (for example, widening the tracks slightly to reduce the resistance or decrease the current density). Or they're used where a handcrafted solution is needed for a critical element. Again, the value of the shape-based algorithm is that these modifications can be made directly on the target net without having to re-route other design sections and using the most up-to-date data.
Over the last four years, the original developers of shape-based routing have been developing a range of tools based around the technology. In some cases, the use of an automated shape-based routing tool like Pulsic's Lyric has greatly reduced the time needed to route an analog chip design. Routing has been done in three hours, for instance, versus the three months that it takes for designs done by hand.
Design For Manufacture
Design-for-manufacture (DFM) tools take the routed design and optimize it for manufacturing in a number of ways. For instance, they smooth the tracks to reduce the number of sharp corners, wire spreading, and wire flattening. In doing so, they also reduce the number of vias. As a result, it's possible to lessen the number of metal layers that are required while cutting the number of mask layers needed and the cost. During all of these tasks, time analyzing will be performed on the layout for the changes in capacitance of the tracks and the changing timing requirement. Such analysis ensures that the changes won't exceed the design margins.
Interestingly, the tool also can be directed to add vias. It can add one or even two vias at each layer transition. As process geometries decrease, the vias shrink in size. The probability of voids within the vias then increases, leading to slower speeds, more signal noise, and even open circuits. Having two or three vias at the transition between layers increases the probability of maintaining the link. It also reduces the resistance, giving higher yields and reliability. The DFM tool can be directed with a back-off strategy. It will try three vias, then two, and fall back to one if necessary.
Wire spreading also is a useful DFM process. After all, current density is a key factor in analog designs. Spreading the wires where possible reduces the current density. It also significantly reduces the problem of lines becoming fuses or even short circuits while enhancing the reliability of the design.
The DFM tool also looks for both long and short lines that can act as antennas when the chip is made. It breaks them up into smaller, non-radiating lines. With mixed-signal designs, this process can be performed interactively on individual lines without having to run a complete new routing. Being able to easily make such changes quickly enhances the manufacturability of the end design. It also improves the yield of the chips (see Figure 2).
Figure 2. Here, a CMOS design is routed with an interactive, shape-based design tool. The expertise of the analog designer is combined with the productivity gains of a design tool.
The algorithm's incremental capability also is a key advantage in reducing the time taken to incorporate engineering change orders (ECOs). If devices have to be added or removed, this step can be done locally. Tracks will be pushed aside and re-routed without having to re-route large areas of the design. Grid-based routers can only handle ECOs this way, which is a key reason behind why project times are longer than expected.
The tools aren't just about routing, however. Consider a shape-based placement tool that allows different shapes other than squares and rectangles to be placed. Such a tool allows legacy and custom elements to be added to a design, optimizing the area that the design occupies. The designer can then use the routing tool to join the elements together. This ability is particularly valuable for elements like VCOs and PLLs.
Such capabilities also lend themselves to extending the performance of the whole device through flip-chip packaging. Being able to route to pads at any location and with any angle requires the ability to have unbiased routing and different track spacings on the top layer. Such capabilities are possible with shape-based tools. They are coupled with the signal-integrity analysis tools to make sure that it actually works.
For the design industry, tackling the challenges of signal integrity and design for manufacture in mixed-signal and analog designs for wireless systems is a key issue. Using an innovative algorithm, such as shape-based routing, allows designers to have more control and analysis of the routing process while it's happening. Through the intrinsic value of the approach, they can converge on the best solution significantly faster than grid-based routing.
This capability enhances the design environment. Design-rule checking and interactive analysis are incorporated to get the design to market faster and cheaper than other approaches. Improving the performance, reducing the area, and improving the yield of a design--particularly in analog designs--are key advantages. They will get a chip profitably to market at the right time for the customer. ◆
Mark Waller is Co-Founder and Vice President of Research and Development at Pulsic Ltd. Previously, he was a Key Developer and Project Leader of IC Place and Route Research at Zuken-Redac Systems Ltd.