Published in issue of Chip Design Magazine

Phase-Locked Loops Are Demystified

By paying close attention to how PLLs are specified, designed, and verified, one can add versatility and avoid delays.

Over the past decade, phase-locked loops (PLLs) have become an integral part of the modern application-specific-integratedcircuit (ASIC) design. PLLs provide the clocks that sequence the operation of the various blocks on an ASIC chip as well as synthesize their communications. There are various types of PLLs targeting specific applications. For example, clockgenerator PLLs are capable of large frequency multiplication. They’re primarily used to generate clocks for digital logic. In contrast, deskew PLLs are used to eliminate clock skew between two clock domains. They’re often used in older synchronous chipto- chip IO applications. Spread-spectrum PLLs slowly vary the clock frequency in order to spread a clock’s electromagnetic (EM) signature over a frequency band, thereby reducing the maximum emitted EM power at any frequency. These spread-spectrum PLLs are used in many consumer products, such as personal computers (PCs) and personal digital assistants (PDAs). It is essential that PLLs be carefully specified, designed, and verified. A poorly designed or improperly used PLL can cause substantial delays in product launch or—in the worst case—total product failure.

PLL architectures are generally grouped into two categories: wideband and narrowband. These definitions are mainly based on the voltage-controlled-oscillator (VCO) topologies that are implemented. Narrowband PLLs generally employ the resonant characteristic of inductors and capacitors to create the VCO. They’re typically used in communications applications that place stringent long-term jitter requirements on the PLL. The improved long-term jitter performance of narrowband PLLs is offset by the narrow frequency tuning range. Usually, that tuning range is only 10% to 20% of the center frequency. A large chip area also is consumed in realizing the inductors. Furthermore, the inductance value will vary from chip to chip as a result of variations in the manufacturing process. The combination of narrow tuning range and varying inductance value necessitates extensive characterization of the VCO to ensure that the target frequency range can be met across all operating process, voltage, and temperature (PVT).

For their part, wideband PLLs avoid using on-chip inductors. The VCOs are commonly built as ring or relaxation oscillators, which use RC delays to establish the clock period. These PLLs have the benefit of a large frequency tuning range (Fmax/Fmin >10X), a relatively small on-chip footprint, and potentially low power. Yet these benefits are offset by the inferior long-term jitter characteristics of such PLLs. Hence, wideband PLLs are seldom used in applications with stringent long-term jitter requirements.


Figure 1: A typical PLL architecture is depicted here.

A typical PLL architecture is shown in Figure 1. The relationship between the output and input frequency is given by:

Fout = Fvco/OD, and
Fvco = Fin*FD/RD, where:
RD is the reference clock divider,
FD is the feedback divider,
OD is the output divider,
Fin is the frequency of the reference clock,
Fvco is the frequency of the VCO, and
Fout is the frequency of the output clock.

PLLs are typically modeled as second- or third-order feedback systems. Some of the key PLL system parameters are: natural frequency or loop bandwidth (Wn), damping factor (zeta), and the 3-dB bandwidth (3-dB BW), which is proportional to Wn*zeta. The lock time of the PLL is proportional to 1/(3-dB BW).

In the typical charge-pump-based PLL shown in Figure 1, Wn and zeta are described as:

Wn^2 = {Icp*Kvco}/{C*N}, and
Zeta^2 = {R^2*C*Icp*Kvco}/{4*N}, where:
Icp is the charge-pump current (A),
Kvco is the gain of the VCO (Hz/V),
C is the main loop filter capacitor (F),
R is the effective resistance (ohms) that is added in series with the main loop filter capacitor to make the loop stable, and N is the FD value.

Other important system parameters of the PLL include static and dynamic supply noise sensitivity, power dissipation, area, duty cycle of the output clock, static phase offset, and—of course— long-term and short-term jitter.

The PLL shown in Figure 1 is inherently a sampled data system, as it only compares reference and feedback edges. For the loop to remain stable, its loop bandwidth, Wn, has to adhere to the following relationship: Fin/(RD*Wn) > 10. For a fast and stable transient response of the loop, the damping factor is typically kept between 0.7 and 1.

Assuming a noise-free reference clock, some of the main contributors to the long-term jitter in wideband PLLs are the VCOs themselves. The main contributors to short-term noise are reference frequency spurs in the output clock frequency spectrum. They are created as a result of charge-pump current mismatches, charge injection, and static phase offsets. For a given VCO frequency, Fvco, increasing Wn will track out more of the noise introduced by the VCO and reduce the long-term jitter. Increasing Wn also will reduce the PLL’s lock time, thereby improving its transient performance. Thus, FD should be kept as small as possible so that Wn is maximized.

Larger FD values also can result in increased short-term jitter. This increase occurs because a larger FD value corresponds to a reduced refresh rate for the loop filter. In the presence of leakage and other mismatches, a large FD can result in increased spurs. In addition to keeping the FD small, spurs can be further reduced by increasing the order of the loop filter. This change is typically implemented by adding an extra capacitor in parallel with the main loop filter (see Figure 2). Increasing the order of the loop filter may require a decrease in Wn, however, thereby resulting in increased long-term jitter. Otherwise, the phase margin of the loop could decrease, which can negatively affect the PLL’s stability. To ensure sufficient phase margin, the size of this extra capacitor is typically made to be less than 5% of the size of the main loop filter capacitor. The previous discussions indicate the existence of a tradeoff between stability and short-term and long-term jitter in PLLs.

In addition to low jitter, the PLL should have optimal transient response across all PVT. To achieve this result, zeta should remain relatively constant across PVT. But it’s impossible to use static control pins to bias the PLL for optimal Wn and zeta across all PVT. After all, the PLL parameters that determine Wn and zeta can show up to a 2X variation over PVT. To address this issue, such a PLL would need to be designed conservatively and would typically have low Wn and—subsequently—large longterm jitter.

One class of PLLs, called self-biased PLLs, relax the constraints that require a lower loop bandwidth. They work by biasing a PLL at its optimal point across all PVTs. This is achieved by using internal feedback to sense the PLL settings and vary the bias points accordingly for optimal performance. In addition, these PLLs can use specialized filters that may eliminate spurs. In doing so, they can significantly relax the long-term/short-term jitter tradeoff. Employing the above principles, it’s possible to provide robust, high-multiply-range (1-to-4096), low-jitter, and low-power PLL hard macros in TSMC, UMC, Chartered, and Common Platform processes from 0.25 um to 55 nm. For details on self-biased PLLs, please refer to the following references. They are available at www.truecircuits.com/white_papers.html

References:

  1. Maneatis, et. al., “Self-Biased High-Bandwidth Low-Jitter 1-to-4096 Multiplier Clock Generator PLL,” IEEE Journal of Solid-State Circuits, Vol. 38, No. 11, Nov. 2003.
  2. Maneatis, et al., “Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques,” IEEE Journal of Solid-State Circuits, Vol. 31, No. 11, Nov. 1996.

John G. Maneatis, Ph.D., is co-founder and president of True Circuits. He holds a B.S. degree in Electrical Engineering and Computer Science from U.C. Berkeley and M.S. and Ph.D. degrees in Electrical Engineering from Stanford University. Maneatis has over 19 years of experience in analog and digital circuit design and is renowned for his work in the area of phase-locked-loop design.

Eskinder Hailu, Ph.D., is a circuit design engineer with True Circuits. He holds a BS degree in Electrical Engineering and Economics from Yale University and M.S. and Ph.D. degrees in Electrical Engineering from Cornell University.


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