Today’s field-programmable gate arrays (FPGAs) contain millions of gates with large embedded memory and complex functions and are becoming as sophisticated as some application-specific integrated circuits (ASICs). As FPGAs continue to increase in capacity, functionality, and performance, FPGA developers are faced with the challenges of meeting increasingly aggressive design goals, such as timing, area, power, and part cost. Completing projects on time is also becoming a larger challenge, due to the complexity of proper verification, the number of design iterations, and the run times of synthesis and place-and-route tools. Clearly, design teams must pick the best design tools to get the job done. There are numerous tools and approaches available for FPGA design today -- some from electronic design automation (EDA) providers and some from the FPGA vendors. Typically, tools supplied by the FPGA vendors are provided at little or no cost to support the design-in of their devices. While these tools may be free or nearly free, they are not without cost. Companies that think that they are saving money by using the free vendor tools often end up paying more than companies that purchased tools from EDA providers. Usually, the cost of a project consists mainly of the cost of the engineers time multiplied by the length of the project plus the material cost of the FPGA devices. Added to this total is the opportunity cost of any delays in getting to the market. The cost of the tools can be spread across multiple projects and often plays a small part in the overall project cost. Given the cost of both engineering time and being late to market, purchasing a toolset that can minimize design time will pay for itself many times over. Moreover, since this toolset is vendor-independent, it can pay further dividends by letting design teams select the vendor with the lowest FPGA cost. EDA companies provide a wide range of vendor-independent tools and methodologies that have been constantly improved for more than the last 20 years to produce the highest quality of results in the shortest time. Tools that raise the level of abstractions (such as using C/C++) allow for faster HDL code generation and architecture exploration. Design-creation tools supporting smart reuse can significantly shorten design creation cycles. Using synthesis tools that provide a high quality of results, gated clock conversion (for ASIC prototyping), automatic incremental design flows, advanced analysis, and debug capabilities, along with superior standards support (such as SystemVerilog and SDC support) can make the difference between completing the project on time or going over budget. And of course, verification and PCB tools are a critical part of any design flow. The free tools from FPGA vendors address a small part of a comprehensive design flow and often cannot compete feature-wise with the offering of a broad-range EDA supplier. FPGA vendors continue to leapfrog each other on price, capacity, speed, functionality, and power. Therefore, we can no longer assume that the best device for today’s project will always come from the vendor used on the last project. Customers must retain the flexibility to target their design to the FPGA device that best matches their design needs. FPGA vendor tools are clearly not designed to let customers easily switch from one vendor to the other. Moreover, these vendors encourage the use of their proprietary intellectual property -- all with the goal of locking the customer to their silicon. In contrast to using the FPGA vendor tools, using vendor-independent tools and coding styles lets engineers easily evaluate multiple vendors for a given project. Often, the optimal solution is to use multiple FPGA devices from different vendors on the same board. Trying to address the vendor-independence issue by using tools from multiple FPGA vendors does not solve the problem. Not only does supporting multiple toolsets present training and maintenance challenges, but doing so prevents objective selection of the best FPGA device. Designers expert in one vendor toolset will balk at learning another, and as a result, will often select an FPGA based on tool preference rather then on the FPGA capabilities. In summary, using vendor-independent methodologies and tools provides for a more productive flow and preserves FPGA freedom of choice. When considering using FPGA vendor tools, designers and management must ask themselves if these tools support their time-to-market and product cost goals and understand the real cost of these “free” tools.