Published on March 24th, 2008
The never-ending goal of making today’s electronic products smaller, faster, and more feature-rich is driving new challenges in system design. Shrinking die sizes and new features are driving IC designers to use smaller process nodes and higher clocks speeds. As more and more functionality is built into the die, the result is increased Input/Output (I/O) count. Reduction in system size also forces smaller area for the package.
From a Printed Circuit Board (PCB) perspective, shrinking product sizes have resulted in smaller form factors, denser circuits, and larger sets of constraints. This has forced smaller area for the packages by reducing pin pitch. Routing smaller PCBs with > 80% of the nets being constrained has resulted in PCBs driving the I/O interface of a package and the need to optimize constraints across different implementation fabrics. The reduced flexibility in system specifications has created a need for tradeoff across IC (chip), package, and board.
Existing package design solutions have a number of very significant limitations.
These limitations and the lack of package design complexity results in a very serial design process.
Figure 1 shows the required steps leading to the creation of the IC footprint used in the package and — eventually — the package footprint used on the PCB. In this bottom-up approach, each of these library components acts as a gate in the process.
Detailed package and PCB design must be delayed, waiting on the required components, thus limiting any significant reductions in design cycle. While it is true that some of the logical PCB design (typically captured in schematics until the advent of Allegro System Architect from Cadence) can run concurrently with the package creation, the routing feasibility of the PCB — which has a critical role in determining the pin out of the package and determining constraints on the package — cannot commence until the package has been incorporated into the board.
To realize significant gains, three critical requirements must be addressed as follows:
The most obvious path to design cycle reduction lies in the ability to create an efficient concurrent design flow. Each environment, IC, Package and PCB, has different flows and are driven by different users who are likely to reside in different locations.
Each individual flow executes asynchronously, so a concurrent process must be able to synchronize changes made concurrently or establish data owners to facilitate smooth synchronization processes. The proposed flow allows each discipline to propose interface changes. The disciplines have the ability to accept or reject these changes and merge them with changes made in the local environment.
Each discipline can validate its interfaces with the others in real time using a synchronization engine. The key to the concurrent design requirement lies in the ability to manage the connectivity of each fabric independently while allowing for concurrent changes that can be easily synchronized between disciplines.
Connectivity for a single die package has never been a tough problem to solve. In most cases, the only reason to use a logical netlist tool was to easily assign an IC bump to a specific package ball. Some designers leveraged standard schematic tools for this process, thus providing a commercial solution for generation of the netlist and management of constraints. As IC and package pin-count grows, however, this approach becomes tedious and error prone. Each high pin-count device must be split across numerous graphical symbols, thereby turning the schematic into a large connect-by-name drawing instead of a meaningful graphical representation.
As pin-counts continued to grow, custom solutions were designed to leverage standard productivity applications such as Microsoft Excel. These solutions required that the user capture connectivity in Excel by encoding signal name to pin number connections into a spreadsheet. For the engineers, this solution was — in many ways — very appealing. They were already familiar with Excel due to tasks such as calculating timing budgets and defining constraint sets. With the flexibility of spreadsheets, this approach lends itself well to complex designs, especially those where more than one die are placed in the package.
Overriding these benefits are a few significant limitations that will result in a limited lifespan for this custom solution as follows:
What is really needed for today’s complex designs is a mixture of these two historic approaches that is also flexible enough to address the concurrent requirements of the IC, Package, and PCB design environment.
The optimal connectivity management solution is one that allows an engineer to perform the following tasks:
Figure 2 shows the roll of the connectivity management system in the solution.
Success in a complex concurrent design process requires adherence to a flow and careful review of the synchronization results along the way. Figure 3 demonstrates the flow and highlights the points where synchronization is critical.
To start the design flow, Verilog from the IC design is provided to the engineer responsible for managing the package connectivity. This Verilog is imported to build an abstract model of the interface. This defines the object to be co-designed between the package and IC environments. Fixed die, bypass, and termination components are added to the design and connectivity is defined in the spreadsheet interface.
A physical netlist is generated and used to define the initial System-in-Package (SiP) database. The physical die co-design process is initiated and the I/O planning environment is seeded with Verilog from the logical design. The I/O ring is placed, a bump matrix is defined, and nets from the Verilog are assigned to the bumps. A Package Interface is defined in layout and package signals can be auto-assigned to the balls.
All I/O assignments and connectivity changes made in the package layout are updated in the connectivity management solution using the synchronization engine.
Using the signals connected to the package, the PCB interface is exported and sent to the PCB environment. The PCB Engineer imports the package interface thus auto-creating a component that can be used in the PCB environment. PCB signals are connected to the component.
A physical PCB netlist is generated and sent to PCB layout. Optimization of the package/PCB interface is carried out now that the package can be evaluated within the context of the board.
The new optimized package interface is updated in the PCB logical environment using the synchronization engine.
The optimized interface is exported from the logical PCB design and imported into the SiP design. This updates the existing package interface, retaining internal connectivity.
A physical netlist is generated and used to update the physical package database. The layout designer must make the decision whether to address the interface changes in package routing or by pushing the change into the IC design.
The final step is to update the IC design in the case where some of the I/O changes are to be implemented in the I/O assignment.
Once these steps have been completed, the IC, Package, and PCB environments are in concurrent design mode. Synchronization occurs by following the standard interface steps defined above. This iterative process allows input from each of the three design environments to ripple through the system and eventually update the other domains.
ECOs can be triggered from any of the points in the process. A common ECO would be the import of a new Verilog into the logical SiP design. This would trigger steps 1-9, which would result in the synchronization of the databases in all three domains.
The complexity of designs today requires a new approach and new solutions for reducing design cycles and optimizing across design fabrics. Old serial processes, minimal integration between design fabrics, and the lack of a common connectivity solution seriously limit the efficiency of design teams.
Today’s designs require new robust design flows with concurrent capabilities that bridge the communication gap between the IC, Package, and PCB environments. The only way to efficiently optimize across these solutions is to enable management of design tradeoffs that are constantly being made in the IC, Package, and PCB domains.
Keith Felton has been at Cadence Design Systems for over eight years in various product marketing roles. His current responsibility is a Group Director of product marketing for the Allegro Advanced IC Package and System-In-Package Design solutions.
Prior to Cadence, Keith held positions at Viewlogic Systems and Racal-Redac in product marketing over an eight year period. Prior to EDA, Keith spent ten years as a systems designer in the wireline telecoms industry.
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