When I was a newly-minted, bright-eyed young engineer, things were so much simpler than they are today. My first job – which commenced in the summer of 1980 – was as a member of a team designing CPUs for mainframe computers. As part of this endeavor, my colleagues and I were tasked with the design of a number of ASICs.
By today’s standards these were incredibly simple beasts. They were implemented at something like the 5 µm technology node and they each contained only a few thousand equivalent gates. This was advantageous, because our design tools at the time comprised only pencil and paper. That’s right – no schematic capture (we drew gate-level schematics by hand), no simulation (we performed peer reviews of each other’s schematics), no automated timing analysis (it was back to the pencil and paper again), and so forth. Looking back, it’s a wonder we actually got anything to work at all, but I digress...
In those days of yore, we chip designers didn’t give any thought whatsoever to the packages in which our chips would reside. Once we’d proved the schematics to our satisfaction, we converted them into textural gate-level netlists by hand, and we then passed these netlists over to the ASIC vendor. Some weeks or months later, a few prototype chips appeared, at which time the fun really started.
Now, although I didn’t think about it at the time, someone in our organization must have specified which pins on the package would correspond to which signals inside the chip. But we never talked about this part of things.
Strange as it may seem, some aspects of this process haven’t changed all that much over the last three decades (good grief, I’m getting old). Even today, while designing the most sophisticated System-on-Chip (SoC) devices, many hardware design engineers focus only on their portion of the chip’s core. Somewhere in the organization is a mysterious group of folks who perform the “chip-finishing” activities – placing the analog and digital modules on the surface of the die, performing chip-level routing, determining power, ground, and input/output (I/P) bump/pad locations, and so forth.
Who are these people? I don’t know because I never met one. Maybe it’s like the strange scientist in the film Independence Day who says rather plaintively: "They don’t let us out very often."
But the times they are “a-changin”. In the case of today’s bleeding-edge SoC devices, it is no longer possible for the chip, package, and board design teams to work in isolation. The problem is that there are so many facets to this that it makes your head spin. Consider a chip containing 2,000 pins, for example, where the I/O placements and bump assignments are performed without considering how the die will interface to the package. In this case, the result may be signal integrity issues, performance issues, increased package size, and an increase in the number of routing layers inside the package. In turn, excessive package complexity can easily push the cost of the package higher than the cost of the silicon chip it contains, thereby rendering the component uneconomical.
Similarly, if the package is designed without considering how it will interface to the circuit board on which it will reside, ineffectively assigned pins on the package can result in problems breaking-out the signals on the board. Once again, this can result in signal integrity issues, performance issues, increased board size, and an increase in the number of routing layers on the board.
And SoC devices are only the tip of the proverbial iceberg. The SoC approach is to create a single humongous die, which is subsequently encased in a package. There are several problems with this tactic, such as the fact that these components are time-consuming (taking anywhere from say 9 to 18 months) and expensive (say $15 to $50 million) to develop and deploy. Also, there are going to be issues with integrating analog and digital functions on the same die, not the least that the cutting edge of digital design is currently at the 45 nm technology node, while the bleeding edge of analog design is only at the 90 nm node. There are also yield issues with larger dies. And yet another consideration is the time and expense involved in re-spinning the design in the future to evolve existing functionality or add new features.
One alternative is 3D die stacking, in which multiple die are stacked on top of each other before being encased in the same package. Another approach is that of System-in-Package (SiP), in which multiple bare die are mounted on a common substrate which is used to connect them all together (this substrate could be formed from a wide variety of materials, from ceramic to laminate). The substrate and its components are then placed in – or build into – a single package. This approach has several advantages, including the fact that one can include analog, digital, and radio frequency (RF) die in the same package, where each die is implemented using that domain’s most appropriate technology process. Also, designers can employ a number of off-the-shelf die coupled, perhaps, with a limited number of relatively small, internally-developed ASICs.
And then there are Package-in-Package (PiP) and Package-on-Package (PoP) scenarios to consider. As I said earlier, there are so many facets with regard to chip-package-board co-design that it fair makes your head spin!
Until recently, chip, package, and board design teams typically worked in relative isolation with very limited communication between them. Actually, when you come to think about it, this is not dissimilar to the way things are (or at least, used to be until very recently) in the EDA companies themselves, in which there was minimal interaction between the folks creating the chip design, package design, and board design tools.
Consider the problem. Inside the chip you have logical signal names that have to be connected to the I/O pads. Inside the package you tend to have equivalent names that are hybrid versions of the names inside the chip and on the board. The chip and package names have to be assigned to each other; also the names inside the package have to be associated with the alpha-numeric pin (or ball) names on the pin grid or ball grid array. Now, the pins (or balls) on the package have to be associated with signal names on the board.
We might visualize this as being a whole series of connectors, with the signal names changing at every level. In the not-so-distant past, the only way to keep track of this sort of thing was to use a spreadsheet. It’s not hard to see how this can quickly become a nightmare when one is dealing with several thousand pins. The result – not surprisingly – was that people were forever misconnecting pins from the chip to the package and the package to the board. One can only imagine the countless wasted hours that have been spent over the years trying to track down this sort of problem.
More recently, however, the big EDA companies have started to wake up and swing into action. One aspect to this that I personally find to be very interesting is the way in which the various companies are all approaching things from different directions, each of which is perfectly valid in its own right.
In the case of the folks from Cadence, for example, the System Connectivity Manager utility – which is part of their System-in-Package Solution for the concurrent co-design of IC, Package, and PCB – reads Verilog netlists from the chip design, pin grid array information from the package design, and layout files from the board design; it performs Layout versus Schematic (LVS) checks from top to bottom; and it allows design teams to communicate across all three domains. During the physical co-design phase, the Cadence SiP solution leverages their digital and custom IC design flows to provide a holistic solution that’s "mask-ready" without translations or interpretations.
By comparison, Magma’s recent acquisition of Rio Design in 2007 has left them with a highly automated chip-package co-design solution that concurrently performs I/O placement and bump assignment on the chip – along with escape analysis and escape routing on the package. The result from the chip side of the fence is optimal die size, optimal bump pitch, and optimal bump assignment to match the package. The result from the package side of the fence is to use the cheapest package with the smallest number of layers and to make all of the assignments in such a way as to minimize any power integrity and signal integrity issues.
And then we have the folks at Mentor, who are leveraging their expertise in the co-design of FPGAs and circuit boards. The idea here is that the assignments of the FPGA’s internal signals to its pins are largely under the control of its designers. The way in which these assignments are performed can either greatly ease the task of the board layout designers or make their lives a nightmare (especially when an FPGA designer swaps a group of pins without telling anyone). In order to address this issue, Mentor have developed I/O Designer, which provides bi-directional integration, data management, automatic pin-swapping, and the ability to perform concurrent FPGA-board design.
Although this isn’t a chip-package-board solution per se, it’s somewhat related in that you are trying to achieve the optimum assignment of pins so as to obtain the maximum routability on the board.
This article has provided only a glimpse into the chip-package-board co-design realm. There are many more facets to this picture than we have considered here; for example, the exotic materials that are sometimes used to form the substrate in SiP packages such as the laminates produced by Rogers Corporation. Also, there are a number of specialist chip-package co-design tools, such as the high-frequency tools offered by Applied Wave Research.
In reality, we are only at the beginning of the chip-package-board co-design era, and we can expect to see a surge of innovative solutions appearing over the next few years. As one simple example, in the case of existing chip-package co-design tools, there’s an underlying assumption that the chip-finishing and package design heroes are either one-and-the-same person or they at least hang out in the same building. In reality, of course, if you were to walk into a room and say: “Put your hands up if you perform both chip-finishing and package design,” very few hands would appear in the air. In fact, in many cases the chip, package, and board design teams reside in completely different countries. So one big challenge is going to be the creating of chip-package-board co-design environments that can handle multiple disparate teams spread around the globe.
Of course, “if it were easy, everybody would be doing it,” as the old saying goes. The point is that chip-package-board co-design is going to affect just about everyone in the not-so-distant future, which is why the iDesign portion of the Chip Design Magazine website is now focused on this arena. Thus, in closing, if you are in any way involved in any aspect of chip-package-board co-design, I’d love to hear from you at firstname.lastname@example.org.
Clive (Max) Maxfield is author of “Bebop to the Boolean Boogie (An Unconventional Guide to Electronics)” and “he Design Warrior’s Guide to FPGAs (Devices, Tools, and Flows)”, Max is also the co-author of “How Computers Do Math” (ISBN: 0471732788) featuring the pedagogical and phantasmagorical virtual DIY Calculator. In addition to being a hero, trendsetter, and leader of fashion, Max is widely regarded as being an expert in all aspects of computing and electronics (at least by his mother). Max was once referred to as “an industry notable” and a “semiconductor design expert” by someone famous who wasn’t prompted, coerced, or remunerated in any way.
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