For years, those clever chaps and chapesses at Apache Design Solutions have been delivering some very cunning solutions with regard to power, noise, and reliability (PNR) signoff for chip, IC package, and system-level designs.

Well, they've just launched a new solution called Sentinel-PI, which they say is the industry's first fully-integrated chip-package-system co-design and co-analysis solution for power integrity.

Sentinel-PI provides SoC-aware modeling and analysis of the system-level power delivery network to enable IC package and PCB designers to optimize their designs, from early stage prototyping to system signoff. This little scamp delivers the following capabilities in a single integrated solution:

• 3D, full-wave power network extraction and power integrity co-analysis engine.
• DC, AC, and transient/dynamic analysis within a single tool.
• Seamlessly integrated Chip Power Model (CPM) for SoC-aware package/board power integrity.

SoC-Aware Package and PCB Power Integrity

Sentinel-PI provides a next generation 3D full-wave power network extraction and power integrity analysis engine optimized for package and PCB designs. The new engine delivers accuracy, performance, and capacity required for a complete chip-package-system co-analysis. From a single product, Sentinel-PI enables designers to perform resistance check and static IR-drop analysis (DC), frequency-domain simulation including impedance analysis of multi-port power delivery network of the chip, package, and board (AC), and time-domain dynamic voltage drop analysis (transient).

The way this works is that once the chip designers have performed their magic, the automatically extracted accurate Chip Power Model (CPM) that they have been working with is seamlessly accessed by Sentinel PI.

Figure 1. CPM is seamlessly embedded in Sentinel-PI.

By embedding CPM, Sentinel-PI enables SoC-aware package/PCB power analysis from early in the design flow and throughout the entire process. During early design, Sentinel-PI enables accurate and predictable package selection, as well as power pad and package decoupling capacitance optimizations. Later in the design flow, Sentinel-PI allows package and PCB designers to accurately run power integrity analysis of the package and the PCB with the power delivery network behaviors of the IC, diagnose potential chip-package LC resonance issues, and validate package/board dynamic voltage noise margin.

The folks at Apache showed me a dramatic example of the impact of using their accurate CPM models with regard to package/PCB power integrity analysis. Using traditional macromodels, the peak IR drop on the PCB appeared to be at one corner of the SoC package. But when a new analysis was performed using the CPM and Sentinel-PI, the peak IR drop was revealed to be in a completely different location.

This really is rather cool. If you want to see more, Apache will be showcasing Sentinel-PI, along with their entire range of power, noise, and reliability solutions for chip-package-system, at the upcoming Design Automation Conference (DAC) in Anaheim, Ca. Until next time, have a good one!