Published on May 29th, 2008
Back in the old days – you know, last century when digital was taking over the world – systems were a mix of standard processors, application-specific standard products (ASSPs), analog circuits, and “glue logic.” Glue logic meant the small- and medium-scale integrated circuits that “glued” together the protocols and buses of the various digital chips. For cost reduction and integration, this glue logic was often swept up into a digital application specific integrated circuit (ASIC).
Today, entire digital systems are being implemented on a few deep submicron (DSM) semiconductors, and “glue logic” has been architected out of the system. But has the need for glue gone away? The answer is yes and no. Digital glue logic is not needed as much as before, but analog “glue functions” are on the rise.
Systems today have many analog functions that do not fit well on 90 and 65nm silicon. These systems require multiple power planes, several voltage levels, power sequencing, sleep mode power, high-voltage LED drivers, quality audio processing, and intelligent control of these functions. The rise of system-on-a-chip (SOC) digital solutions has led to the need for mixed-signal ASICs, to sweep up a variety of analog functions for costs savings, performance, and integration, as shown in Figure 1.
Figure 1 - Discrete power management functions combined in a via-configurable ASIC
Portable electronic devices may include a wide range of supply voltages: 1.8V and 3.3V for digital ICs, 4.2V for a Lithium-ion battery, 5V for legacy interfaces, 36V for LED backlighting, isolated voltages for sensitive analog circuits, and high voltages for motor control. Designers choose among various power-conversion topologies including linear, switching, and low drop out (LDO) regulators, depending on the requirements for each power source. Not only is the sheer number of regulators increasing, but these systems often have intricate power sequencing requirements that demand precise control of the turning on and off of each supply with regard to one another during the power on, power off, sleep, and brown-out modes of operation. Often these supplies don’t simply turn on, but instead require soft ramp-up/down behavior of supply voltages, adding additional complexity to the power management system. Along with getting the regulator voltages sequenced correctly with each other, system reset signals and oscillator turn-on and PLL stabilization times must be accounted for in the power management architecture of the device.
A power management system integrates various power conversion topologies, digital sequencing logic, and digital communications to control the power management functions, and analog voltage and current measurement; and non-volatile memory to store voltage set points, sequence order, sequencing time periods, and factory calibration data. These power management resources consume lots of board space, require multiple packages, and add to assembly costs, making them ideal candidates for integration into a power management integrated circuit or PMIC ASIC. These ASICs are fabricated on a mixed-signal process so functions not normally associated with power management – such as audio processing, buzzer drivers and motor control – become candidates for inclusion in the device. It is not uncommon for a PMIC ASIC to be responsible for integrating and controlling many of the IP blocks and functions shown in Table 1.
Sweeping all the analog and power management “glue” into a single device achieves integration, improves sequencing performance, and reduces overall system cost. However, full custom power management ASIC development historically has been expensive, slow-to-market, and pretty risky.
Recent advances in via-configurable array (VCA) technology have resulted in silicon-proven power management ASIC solutions that can be configured and customized to a particular application through a single mask layer change. A VCA combines silicon-proven analog, digital, and memory resources onto an ASIC die. These resources are then overlaid with a global routing fabric. Wafers containing these VCA die are partially processed and staged at the foundry. All of the analog and digital resources can be interconnected and configured by a single mask layer of vias. Since only one mask layer is processed at the foundry, fabrication costs are greatly reduced, fabrication time goes from months to weeks, and the use of silicon-proven IP and interconnect routing greatly reduces risk.
An available via-configurable PMIC device is the shown in Figure 2 and incorporates the building blocks shown in Table 2.
Figure 2 – Via-Configurable Power Management ASIC from Triad Semiconductor
Developing an integrated power management solution inside a via-configurable ASIC follows the flow outlined in Figure 3 and begins with determining the system’s required voltage domains, the active and sleep mode current requirements for each domain and the sequencing of supply voltages. The PMIC design intent is captured as analog schematics and digital HDL. The high-level design is then simulated to confirm device operation. In a traditional full-custom ASIC design flow, the next step would be the laborious, expensive, and error-prone process of manual transistor layout required to translate the design to silicon. In a via-configurable flow, the digital design described in HDL-format is synthesized to Verilog gates and software is used to translate the SPICE netlists from the analog schematics in gate-level Verilog. The analog and digital Verilog netlists then are combined and submitted to a via-only automatic place and route tool that places vias throughout the global routing fabric to configure the device automatically. The mixed-signal automatic place and route process completely configures the device in days, compared to the months required for full custom power management IC design. The output of the place and route tool is a GDSII representation of the via mask layer between the global routing metal layers. This routing layer is sent to the foundry where only one mask needs to be fabricated versus the 20+ layers needed for a full custom design, significantly reducing fabrication charges and enabling prototypes in weeks versus months.
Figure 3 - Via Configurable Power Management ASIC Design Flow
Configurable ASIC providers are providing designers with silicon-proven power management and mixed-signal IP building blocks integrated onto via-configurable ASICs. Coupling known and good IP with a “no-full-custom-layout-needed” approach to IC design is resulting in low-cost, rapid development, and a safer design flow. It thus enables design teams to provide solutions for the challenging and ever-changing power management solutions needed for today’s products.
Reid Wender, director of application engineering, joined Triad Semiconductor in 2005. Previously, he was vice president of engineering for the Semiconductor Division at QuVIS. He has 20 years of ASIC design and project management experience at companies including Nextwave Silicon, ASIC International, Philips, and IBM, and holds a BSEE degree from the University of Tennessee.
Are you up-to-date on important SoC and IP design trends, analysis and market forecasts?
Chip Design now offers customized market research services.
For more information contact Jenna Johnson at 612.598.3446
Austin, TX June 5-9, 2016
Encore at the Wynn, Las Vegas June 12-15, 2016
Red Rock Resort & Spa - Las Vegas, NV June 23-24, 2016
Moscone Center - San Francisco, CA July 12-14, 2016
Hyatt Regency - Santa Clara, CA July 26 - 27, 2016