Although its adoption rate has been slow in past years, transaction-based acceleration (TBA) methodology is (1) catching on, and (2) evolving fast. TBA 2.0, which is SCE-MI 2.0 draft standard compliant, tackles a common problem in verification environments where a testbench and hardware-based emulator must communicate in real time with maximum efficiency. While both sides of the set-up are likely to perform their task well, the verification process tends to get bogged down by an inability for the two environments to work together – or at best a slow signal level communication between the two.
TBA 2.0 presents very fast transaction-level communication between the DUV and testbench. The approach also introduces the benefits of re-usability. That is, you can implement a simulation-like environment with full congruency to compress your learning curve and speed migration to TBA 2.0 methodology.
Figure 1: Transaction-based acceleration methodology provides significant performance improvement allowing very fast transaction level communication between the DUV and the testbench.
The diagram above delivers some insight into what the TBA 2.0 process looks like. Essentially, communication between the workstation and the accelerator/emulator is minimized. The workstation sends lightweight commands in the form of SystemC transactions to the hardware where the BFM translates the transactions. Only abstracted testbench components remain on the workstation.
The BFM, DUT, and assertion Protocol Monitor are all accelerated. The system is now capable of delivering 100X or greater performance on a two million gate design compared to simple workstation-based simulation. Higher performance is possible on larger designs.
It’s remarkably easy to understand how hardware-based verification with TBA 2.0 delivers increased ROI. Hardware and system/software bugs are normally found too late in the cycle during validation, using prototyping. With in-circuit emulation, hardware bugs are found much earlier in the overall process, including full software and system validation. By utilizing TBA 2.0 users are implement techniques much earlier in the design cycle, that with in-circuit emulation and can typically shave multiple months off the overall schedule saving a huge amount of precious development time.
TBA 2.0 also introduces 100% congruency between simulation and acceleration by utilizing uniform SystemC or Specman-based testbench Native interfaces for both. In simple terms users can verify a design with a standard simulation based verification testbench and access valueable acceleration to speed the testing process when needed. Users of simulation will experience and enjoy a very fast learning curve because of the familiarity of the simulation envronment. Congruent VIP (assertion monitors and transactors) is also used for simulation and acceleration boosting the value of your verification IP. You can also stick with the same simulator for all transactor development, which helps keep development costs in check.
During testbench and model creation, the use of native interfaces to C/C++, SystemC and “e” make your development environment easy to use. A native blocking option is highly useful for modeling input push transactors with a dramatically simpler modeling ease. Proxy modeling now becomes a simple e interface, or a standard OSCI 2.0 TLM standard support with SystemC to simplify modeling issues. Complete transaction objects are transferred in one operation and large variable length transactions are automated. Modification of the proxy side of a transactor to support other Hardware Verification Lanquages (HVL) like SystemVerilog can be accomplished in a much more simplistic manner.
Direct TLM interface capability built into TBA 2.0, highlights how the special considerations for supporting other abstraction levels. This feature allows users to quickly migrate their existing C/C++/SystemC environments, that is used for performance measurement and architectural exploration long before RTL of the design is coded, in a much easier and simpler way. Direct TLM interface allows users to even combine pure high-speed TLM models in the same homoegenous verification enviroment with TBA 2.0 transaction-based acceleration VIP for rapid access to hardware acceleration early into the design and verification cycle.
Highly reactive flows can deliver quicker more effective debug and design turns, while the ability to effortlessly switch to streaming flows, allows quick performance optimization of regression test environments.
Major productivity can also be achieved with other features like automated variable length messaging, timed testbench support, contrained-randomization along with automatic transaction recording to get to market faster with higher quality.
With TBA, you can incorporate highly efficient plan-driven verification techniquest that allow users to really take advantage of the automation to make processes more predictable and reach verification closure faster.
By creating a system level verification plan including integration of all the block level verification components, users will have direct access to many of the benefits including system-related features such as system level assertions, additional coverage items, and directed tests. Reusable verification components from block level verification plans are identified, and by doing so, you eliminate use cases that are covered at the block level. You also add TBA acceleration/ regression attributes such as long test scenarios, streaming interfaces, and stimulus pre-generation.
Throughout the process, detailed reports indicate which features have or have not been exercised. As coverage goals are achieved, the information is annotated back to the feature-based and overall system-level plan so verification managers can analyze exactly what remains to be done to achieve accelerated verification closure.
With TBA 2.0, you can view test results at the source code, transaction level and even signal level, with one window to help you focus on what is happening at all levels of functionality. All the signal level features are still supported, so you can view transactions and individual signals side-by-side and dive into the transaction details or source code at any time.
Debugging at the transaction level means you can see the event as a read cycle with specific data. Instead of repeatedly being forced to examine “how,” you can focus more on “what” is happening. Because transaction relationships are also recorded, you identify unexpected transactions and can see the associated transactions. This ability gives you the power to look at the simulation from a functional perspective. You’re able to raise the level of abstraction as well as link specific stimulus to their results.
A unique hybrid mode combines TBA 2.0 with in-circuit emulation. Two clock domains are required. A non-stop clock domain is used for communicating with the dynamic charges. A stoppable clock domain communicates with the TBA interface. Progressing through each mode adds access to more stimulus and real-world verification. The hybrid mode enables a combination of TBA and in-circuit emulation in a single configuration allowing you to migrate from one to another.
TBA 2.0 delivers impressive time savings with performance enhancements from 100X up to 10,000X. By using the methodology, you drastically reduce debug schedules by shortening simulation cycles. You’re better equipped to locate bugs in RTL long before the entire system level is implemented in in-circuit emulation. TBA 2.0 enables you to re-use much of your testbench methodology, take full advantage of behavioral modeling extraction, and work with a highly integrated debug environment, which amounts to an accelerated time to market for your complex devices.
Kevin Donovan has been a Sr. Product Marketing Manager for hardware emulation and acceleration at Cadence Design Systems for more than four years. He has more than twenty five years experience in engineering design, marketing and sales in the electronics high technology industry for companies such as Synopsys, LTX Corp. and Hughes Aircraft.
Are you up-to-date on important SoC and IP design trends, analysis and market forecasts?
Chip Design now offers customized market research services.
For more information contact Karen Popp at +1 415-305-5557
Seattle, Washington October 21-23, 2014
Irvine, CA October 22-23, 2014
San Francisco, CA December 13-17, 2014
Santa Clara, CA January 27-30, 2015
San Francisco, CA February 22-26, 2015
San Jose, CA March 2-5, 2015
Grenoble, France March 9-13, 2015