Published on October 01st, 2008

Why Is the GSA’s New AMS/RF Process Checklist Useful?

David Schwan Why is GSA’s new Analog/Mixed-Signal/Radio Frequency (AMS/RF) Process Checklist of use to an Intellectual Property (IP) designer or IP integrator?

Scenario 1: You are a marketing manager at a small IP company, and you’ve been tasked with determining whether your IP block can be ported to process “X” and to another foundry at the request of one of your customers. You locate two stacks of foundry documents — one for the existing process in which the IP block is in, and another for the target process — and begin the tedious practice of looking for commonality between the two processes.

Scenario 2: You are a design manager exploring the feasibility of having an IP block transferred to another process. Similar to the first scenario, you spend countless hours searching through a myriad of documents to gather the necessary information.

The GSA Analog/Mixed-Signal/Radio Frequency (AMS/RF) Process Checklist provides an option to collect this necessary information, because it provides a consistent summary of the most important information describing an AMS/RF semiconductor process.

The checklist is comprised of seven key sections:

  1. Process Type — A high-level overview of what is included in the process
  2. Process Release Status — The release status of the process, including rules, prototyping availability, and if the process is fully qualified and in production
  3. Process Attributes — Non-device related features of the process (e.g. number of metal layers or what power supply voltages are available)
  4. Passive Device Attributes — Electrical specifications for each passive device included in the process
  5. Foundry Logistics — Details about masks and wafers
  6. Active Device Attributes — Electrical specifications for each supported active device
  7. Libraries and IP — A brief summary of the digital IP blocks available

The Process Type section includes the type of process (e.g. CMOS, RFCMOS or BCD); an overview of the available devices in the process (e.g. active devices, such as NMOS and LDNMOS, or passive devices such as resistors, capacitors or inductors); and whether the supported devices are either parameterized cells or fixed cell instances.

The Process Attributes section includes process attribute descriptions: Gate size (e.g. 65-micron), the number of metal layers and their thickness, dielectric material type and thickness, passivation material, logic voltages supported, available well options, if multi-Vt transistors are supported, bulk sheet resistivity, and whether flip-chip back-end processing exists. These questions give a summary of both device-specific and non-device specific options.

Passive Devices Attributes provides detailed information about what types of resistors, capacitors, diodes and inductors exist. Important parameters such as sheet rho, temperature dependency (TC) and capacitance per unit area (F/micron2) are included.

Foundry Logistics answers common questions about masks and ordering wafers. The number of mask layers, hot lot availability, wafer size, supported fabs (if a foundry runs the process on more than one line) and lot size are discussed.

Active Device Attributes provides basic information about each supported active device. Parameters such as the Ft of transistors, breakdown voltages and Vts of various MOS devices are found here.

The last section, Libraries and IP, provides a brief description of the digital standard cell-based IP that might be available. Included are standard cell library; memory compilers for SRAM, ROM and non-volatile memory blocks; input/output (I/O) cells; and basic analog blocks, such as: phase-locked loops (PLLs), bandgap regulators, analog-to-digital (A/D) or digital-to-analog (D/A) converters. Specifications such as the number of routing rows for standard cells or the pitch of the I/O cells are documented in this section.

As a result of having the process description contained in a short checklist and with the consistent format of the specifications, the previously tedious comparisons can be accomplished in a shorter amount of time for those companies that have adopted a fabless, fab-lite or integrated device manufacturing (IDM) model.

David Schwan is a CAD and Layout Manager for RFMD and works in the Multi-Market Product group (formerly Sirenza Microdevices). He is the author of numerous papers in CAD methodology and IP, and has two patents pending. He is a member of the GSA mixed-signal subcommittee, and is an active participant in the GSA IP ecosystem.



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