Published in September / August 2008 issue of Chip Design Magazine
[No Respins] SystemC TLM-2.0 Becomes Virtual Reality for Software Developers
There has been much debate about hardware design languages over the past couple of decades. Just over 10 years after the VHDL vs. Verilog wars, the industry has moved up to the next level: today, both SystemVerilog and SystemC are universally supported by simulators across major companies, enabling users to realize productivity improvements in both hardware design and verification.
Over the last couple of years, however, the new reality has set in that software development is becoming increasingly important because it determines both the cost and the associated chip-design schedule. At 90nm, for example, the typical overall chip-related development effort for software has already surpassed the effort for hardware. For 45nm designs in the year 2011, market-research firm International Business Strategies, Inc. projects that less than 40 percent of the overall development efforts will be spent on hardware. This is a pivotal trend and has caused enough user pressure to drive virtual platform related standardization as part of the Open SystemC Initiative (OSCI).
Have SystemC virtual platforms failed to meet software programmers’ expectations in the past? Absolutely! Although the intent of the early proponents of SystemC has always been to support “Software Development”, until recently, SystemC has not possessed all the necessary technology components, for a variety of reasons. Within the Transaction-Level Modeling (TLM) working group, several different abstraction levels were introduced without clear guidance about how to use the models. The varying abstraction levels left some users confused, forcing them to create custom derivatives to address specific needs. In addition, the level of abstraction of processor models was typically dictated by hardware designers and often included more detail than software programmers really needed. As a result, execution speeds were in the single-MIPS or even sub-MIPS range, which is far too slow to serve the needs of most software programmers.
In the past decade, proprietary solutions for virtual platforms designed to accelerate early software development have been introduced by several companies, including AXYS Design Automation, CoWare, VaST, Virtio (now Synopsys) and Virtutech. In the absence of standards, the technology components required for fast virtual platform execution have been realized using proprietary implementations. For starters, it was crucial that the virtual platform models were at an abstraction level accurate enough to enable binary compatibility of software developed on a virtual prototype with the real hardware, while also omitting enough detail to allow fast simulation. Next, different processors in a multi- core system were loosely coupled to run freely and synchronize only at borders of larger units – e.g., every 1000 or 10,000 executed instructions. Finally, proprietary back-door accesses allow models to directly access memory without having to cause transactions within the simulation infrastructure. As a result, virtual platforms were able to run above 50MIPS and, sometimes, even reach several 100MIPS of execution speed.
Over the last two years in particular, users and vendors have realized that “it’s all about the models,” and that model interoperability is key to maintaining and growing a healthy virtual prototyping industry. Important donations to OSCI’s TLM working group have evolved into the draft TLM-2 standard, which contains technology elements for loosely timed modeling, direct memory interfaces (DMI) and temporal decoupling the transaction abstractions so that all virtual platform components can communicate and be interoperable. The draft standard has passed public review and is on track to be ratified mid- year 2008 and subsequently contributed to IEEE. At the most recent North American SystemC User Group meeting, TLM-2 early adopters reported processor-based platforms running at 250MIPS utilizing SystemC TLM-2.
The magnitude of this standardization is equivalent to the introduction of Verilog in the late 1980s – leading to the eventual demise of proprietary languages like HiLo, DABL, UDL / I and n dot. SystemC TLM-2 is the key enabler for a standards-based virtual platform ecosystem with model interoperability and, going forward, will serve as the bridge between hardware and software design.
Marketing, at Synopsys, Inc., is responsible for
the System-Level Solutions products Innovator,
DesignWare System-Level Library and System
Studio with a focus on virtual platforms for
early software development. Prior to joining
Synopsys, Frank held senior management
positions at Imperas, ChipVision, Cadence,
AXYS Design Automation and SICAN Microelectronics.