Turning the Power On at the System-Level for Power Analysis and ExplorationNewer technologies bring much needed help to system-level designers concerned with system-level power requirements and trade-offs.
In a relatively short time, power issues have quickly moved up the priority list for many systems designers planning for the next generation of System-on-Chip (SoC) devices. Project teams can no longer afford to disregard power trade-offs because the risks are just too high. For many, the problem lies in the fact that they “over spec” the design at the system-level and choose to go with a conservative package to be “safe”. Unfortunately, “over spec-ing” and “playing it safe” may lead to unnecessary increases in costs and potential schedule delays.
On the opposite side of the coin, teams have a tendency to underestimate the overall effort involved with accurately designing and verifying power intent, which more often than not leads to device failures and – in the worst case – product recalls. If these products somehow avoid a recall, the outcome can still be grim and costly. Issues associated with an over-constrained power design include to time to market delays and low yields that can wreak havoc on critical projects. The time is right for holistic technology that pays close attention to power issues targeted at SoC designs. These solutions must offer project teams the ability to make educated power trade-offs and get it right early and often. How do we go about doing that?
First of all, teams need to select their IP much earlier at the system level. The IP has to take into account all the various constraints related to power, and also to support the verification flow inclusive of power intent. These solutions must also offer improved ways to measure power dynamically at the system level in real-world scenarios and allow for effective power exploration. This includes having the ability to better-estimate power demands, measure results, and iterate as necessary. Teams need to address productivity concerns by assessing inconsistent power views across a flow that relates back to different files, interfaces and various metrics gathered throughout the project. If these issues are not closely managed, the overall design flow becomes fragmented and hard to use leading to painful and costly failures.
Project teams also need to be able to more accurately predict these system-level outcomes, accounting for not only the hardware, but also the software. This establishes a cohesive and inclusive path within the hardware and software domains offering a much higher likelihood of remaining on schedule and ensuring success. If power is not a priority or given much attention early in the flow, we’ll continue to see mismatches between the system-level intent and the final signoff. This is clearly not what development teams want to deal with and must be addressed with new technologies.
Chip-Level Power Exploration and Dynamic Power Analysis
One way to address these issues is to have ways to better formulate the power intent at the chip and system level. By allowing rapid exploration and options for “what-if” power analysis, teams will have a much better awareness of what they are up against regarding power trade-offs.
One way to do that is with technology like Cadence’s Incyte Chip Estimator. This solution allows users to estimate and create graphical or tabular representation of the power architecture. It also enables users to interactively manage power domains and specify components within those domains. This technology also helps to define functional modes, explore cost benefits of advanced low power techniques such as power shut-off, and multiple supply voltage issues to drive power intent into downstream tools and solutions. This allows teams to better quantify overall “costs” and address ROI early in the process when it matters most.
Another way to address power issues is with Dynamic Power Analysis (DPA) that works within emulation systems such as Cadence’s Palladium III system. DPA adds a level of intelligence to identify, capture and analyze power switching activities for peak and average power analysis giving users much more visibility into the overall system. This quick estimation of power consumption at the system level during the design phase includes analyzing the affects of software and other real word stimuli. This type of system offers tremendous throughput and is cycle accurate to dynamically measure SoC power consumption while running pre-silicon scenarios with the embedded software. With this higher visibility into power dissipation within a realistic environment teams have a much higher degree of confidence when deciding between the overall power budget and expected performance, allowing for better planning at the chip and system level needs.
The time is right to address system-level power analysis and exploration. It will take newer technologies working together to address these needs. Cadence’s Incyte Chip Estimator and the recently announced Dynamic Power Analysis capability will bring much needed help to system-level designers searching for ways improve system level power requirements and trade-offs.
Michael Munsey has 20 years of experience in design and EDA and is currently Director of Advanced Verification Product Marketing at Cadence focusing on low power design and verification.
Michael first cut his teeth on low power design challenges as a design engineer at IBM and later brought that experience as one of the early employees of Senté where he was involved in application engineering, sales, business development and marketing. Prior to Cadence, Michael was Vice President of Marketing at Silicon Dimensions and also has held sales and marketing positions at Sequence Design and VIEWlogic.