Published on January 29th, 2009
There used to be two ways to prototype ASICs. After deciding on your IP and working out your design, you could complete your simulations and release masks to either a multi-project wafer (MPW) or to a full mask set. Customers then had a difficult decision to make — to enjoy the MPW’s low cost also meant delaying the purchase of the full mask set, but that cost did not go away. So based upon the confidence the design team had with the design, and the ever-present schedule pressures, either the MPW or the full layer custom tapeout would be selected.
The silicon verification situation became more complex with FPGAs entering the mainstream for ASIC prototyping due to their combination of high speed verification and quick design iterations. Not to be outdone, structured ASICs came into being offering a new compromise in terms of performance, NRE, and schedule. The most recent innovation in this space has been the rise of the multi-layer mask, offering an option that combines full custom silicon levels of performance and cheaper masks, but with higher unit costs.
Multi-layer masks leverage a single mask to represent multiple layers of the design, reducing the total number of masks needed, and thereby the total mask cost. However, there is a tradeoff: the processing requires more foundry time on the steppers since you are exposing less of the wafer with each step. In the figure, you can see that exposing a wafer with a MLM will take four times as long as with a traditional mask, since you are exposing one fourth of the area with each step. The net result of this slower foundry processing is higher wafer costs.
Figure: Multi-layer masks reduce the total number of masks but require more foundry time to create.
So, how should today’s customers balance schedule, design confidence, and mask cost to make the right decisions about how to tape out their products?
First and easiest, let’s consider schedule. Customers needing the fastest possible path to high volume production will have to go directly to a full mask set. For small, simple designs with high confidence of first pass success, the risk of this may not be too great. Also, for designs in 130nm and older processes, the mask costs are likely not too high should the design require an all-layer change. Otherwise, the risk could be substantial to get the fastest possible schedule. One other option to consider to defer risk without compromising schedule is to tape out a subset of the design early to a MPW to prove out particularly risky blocks, such as new first-use IP and design blocks, in parallel with the rest of chip integration and verification effort. Since only a subset of the design will be on the test chip, a MPW is a great option.
For designs with a little more time before high volume production, either a whole-chip MPW or an MLM tapeout may make sense as they deliver working prototypes at reduced cost, with the caveat that neither is suitable for high volume. An MPW can get you a few hundred extra parts for an early production run, demo units, or customer samples, but more devices than that quickly becomes cost prohibitive. The MLM can actually run in low-volume production, offering more devices and therefore more flexibility. A MLM has in general about the same processing cycle time as a MPW, although the MLM has the advantage of starting whenever the customer needs, vs. on a fixed foundry schedule.
Die size also plays heavily into this decision. First of all, consider MPWs. An MPW will have a tile size for each process. Translating those tiles into an estimated gate count:
|Estimate of gates fitting into a tile, assuming no IP or memory||1.3M||2.3M||2.9M||3.5M||4.6M|
Designs larger than the tile size (for example, a 3M gate 90nm device in the table above) will pay a surcharge. Although billing has changed so that tiles are now prorated based upon die area, still a large die could require area equivalent to many tiles and the surcharge could become cost prohibitive.
For MLMs, there is also a die size consideration. A design can only be about 12x15mm and still fit on a mask 4 times, with current 300mm foundry technology. So, for the very lowest cost, you will need to use an MPW for the smallest designs, and MLM for midsize designs, and a full mask set for large designs. A table summarizing the die size options is presented here, where “x” is the die size of one side of a square die:
|Use MPW?||Use MLM?||Full Mask Set|
|40nm||x < 8.1mm||8.1mm < x < 12.0mm||x > 12.0mm|
|65nm||x < 8.5mm||8.5mm < x < 12.0mm||x > 12.0mm|
|90nm||x < 7.6mm||7.6mm < x < 12.0mm||x > 12.0mm|
|130nm||x < 7.3mm||7.3mm < x < 12.0mm||x > 12.0mm|
|Cost left?||Full Mask Set||Full Mask Set||-|
|Extra Protos||High Cost||Low Cost||Production Cost|
Not only do MPW and MLM prototypes save money on prototype mask costs, they may also save that money a few times over if a few respins are needed on a complex design. Also, for low volume programs, an MLM start can be particularly effective as typically up to 120 wafers can be purchased at higher MLM wafer costs with an overall program cost savings, due to the cheaper mask set cost up front. Finally, for programs needing several thousand prototypes, MLM offers a unique value even for small die with its ability to provide reasonable volumes off of the prototype mask set. With MLM and MPW options, designers now have a richer selection of choices for trading off schedule, risk, and cost when prototyping their device.
Colin Baldwin is Open-Silicon’s Director of Marketing. He has 15 years of ASIC design and sales experience with Texas Instruments, Arrow Electronics, and Open-Silicon. Currently he is focused on marketing and business development activities for Open-Silicon. Mr. Baldwin received both BEE and MSEE degrees from Georgia Tech.