Published on February 16th, 2009
Here’s the scenario: You have 65-nm prototypes back on your latest chip and you notice something odd. Your Application Specific Integrated Circuit (ASIC) vendor says that all of the parts that it sent to you are good. Yet you have one die that burns 100 mW and another seemingly identical die that burns 1 W. How can they both be good? How can they differ by so much? You ask for a power-consumption screen for the test floor to go with your at-speed testing screen. Who pays for that yield fallout?
The big issue in the ’90s was performance. That concern gave way to a focus on power as the top problem for the early 2000s. Now, it’s time to confront the chief villain of today: variability. Lithography limitations and atomistic doping mean that performance and leakage power now vary tremendously across otherwise good die. Your choice is to either tune the silicon to tighten the distribution or put a painful screen in place and throw out a lot of defect-free devices for being parametrically out of bounds. Back in 2006, Blaze DFM said, "At 65 nm, parametric failures—i.e., chips that fail to meet power and timing specifications—have become dominant."
A solution does exist, however. Since 2001, a technology called transistor back biasing (also body biasing or substrate biasing) has been proven to reduce subthreshold leakage. Early studies showed that the voltage applied to the body node of a CMOS transistor was like stomping on the gas pedal in a car or taking one’s foot off the gas. If the chip was faster and leakier than its neighbors, back biasing allowed you to slow it down a bit while cutting leakage power by 30% to 50%. That means that those bad parts are good again and costs just went down.
Like many promising technologies, back biasing comes with challenges. Not only do n-channel and p-channel FETs act differently in the presence of bias, but also so do transistors with different beta values and with different voltage thresholds. The presence of a bias voltage also requires taking a look at how ESD was managed on the chip, as we do not want to see any parasitic diodes turning on unexpectedly. With additional bias voltages we also end up with about twice the analysis corners for signoff. Finally, where do the bias voltages come from, anyway? The n-channel FET will want a bias supply that is below ground, which most systems do not have.
Despite these challenges, many chips today in ultra-high-volume spaces, such as mobile phones, already use back biasing. Altera’s recently announced 40-nm field-programmable gate arrays (FPGAs) include back biasing, showing that it isn’t just for cell phones anymore. Until recently, however, back biasing hasn’t been available to ASICs. Last year, Open-Silicon’s VariMAX technology made back biasing available to TSMC and Common Platform ASIC designs in 65 and 40/45 nm.
These various users actually use back biasing in several different ways to manage variability. The first method is to reduce leakage in standby mode. Think back to the gas-pedal analogy used previously. When a chip is put in standby mode, a back bias is applied to reduce the leakage power. When the part needs to return to active mode, the bias is removed and full performance is restored.
A second method is for performance. When ultra-high performance is needed, one can stomp on the gas pedal and crank up that device. Yes, it will leak a lot. But for some folks, it’s the pure horsepower that matters.
A third method is programmable back biasing. To manage variability, the chip is first tested to see how fast it is. Some “just-fast-enough” parts are left alone. But really fast and leaky parts receive some bias to slow them down and reduce that subthreshold leakage. By varying the bias applied, the wide distribution of raw parts can be tuned into one or two target buckets, thereby improving yields and reducing power.
Back biasing is a promising technology that can not only improve leakage power consumption, but also tune a distribution of parts so that manufacturing variability does not cause a spike in device costs as a result of throwing high-power parts away. Today’s engineering teams need to make the decision to bias their devices, make them usable, and ship them in volume.