For well-characterized integrated circuits (ICs), such as those with feature sizes of 90 nm and greater, production yield losses are usually related to manufacturing-process variations. Such causes are relatively easy to identify, as products tend to ramp to volume quickly. Any expected manufacturing variability that may cause defects is taken into account with design rules. In addition, a compliant design is expected to produce within “entitled” yield rates. At design nodes below 90 nm, however, little margin exists between design rules and manufacturing-process variations. For mature products—those that have been in production for as long as 12 to 18 months—the expected yield is reduced by an average of 5% with each successively smaller design node. Before mature yield levels are reached, the yield ramp for new processes and products can be erratic.

At these advanced nodes, unexpected interactions between design features and manufacturing variability are causing an increase in yield-limiting defects. These defects may be design or feature related. They are harder to identify because they haven’t been well characterized. The defects can look as if they’re randomly distributed across the wafer and lots. Because the defective dies are likely “hidden” in random patterns across the wafer, it’s difficult to identify the devices that are actually being affected by systematic issues.

Optical resolution also has become an issue when manufacturing advanced designs with smaller feature sizes and more metal layers. As a result, it’s more difficult to make visual identification during failure analysis. Another growing challenge lies in narrowing down a defect’s location based on the analysis of test signatures and manufacturing data.

Engineers at fabless companies may not have access to manufacturing equipment data, the results of optical inspection tests, or wafer-position data. In this situation, the root cause of systematic yield-limiting defects has to be determined without all of the data that traditionally has been available to integrated device manufacturers (IDMs). Failure analysis will therefore require additional time, effort, and money.

Faster Path To Root Cause Of Failures
In the past, only the pass/fail information from the manufacturing test was applied to failure analysis and yield learning. Before logic diagnosis software was available, detailed test-failure information wasn’t used. It simply wasn’t feasible to analyze the information manually. Instead, the failure-analysis process was often ad-hoc. Even the task of selecting which die to open up to analyze was a big challenge. Getting to the root cause of failures could take many days or even weeks.

An approach that uses volume diagnosis provides a faster route to finding the root cause of IC failures. It uses the detailed data generated by manufacturing test. This information can include not just which test pattern failed, but exactly which ones out of millions of test-pattern cycles caught the failure—and at what pins. For high throughput, the diagnosis tool needs to be able to work with on-chip test-compression logic. As a result, there isn’t a problem of deciphering the compressed test data.

Scan-test diagnosis software helps to determine what the possible physical causes of the failure might be and where they might be located in the physical layout—including on what layer. The software generates diagnosis reports for each failed die. These reports, in turn, can be used to group the die based on the matching of specific failures, such as bridges, opens, cell, metal layers, etc.

Failures can be categorized in various ways. Defect suspect classifications from scan diagnosis include cell-internal failure, open, bridge, and slow defects. Some die will contain multiple failure suspects, which will be ranked by probability scores. If too many suspects are returned in the initial diagnosis results, an offline process called iterative diagnosis can be invoked. In that process, additional test patterns are created to target the design areas around the defect suspects. These new test patterns are run on the tester against the failing devices to capture new failure files. Those files are then brought back into the diagnosis tool. With the additional information, the tool is able to reduce the number of defect suspects (see Figure 1).

The volume diagnosis methodology is more accurate, has higher resolution, and provides more meaningful suspect locations if it is “layout-aware.” In other words, the diagnosis results should be based on the manufacturing test set along with design and layout data. By incorporating the layout information into automated diagnosis and yield analysis, the type of defect can be identified and localized—down to its physical coordinates—much more quickly than can be done manually.

With a net open defect, for example, layout-aware diagnosis can specify the branch of a net on which the defect is located. This capability can save huge amounts of failure-analysis time, as some nets consist of many branches that traverse long distances across the die. Rather than telling the failure-analysis engineer to find the defect on a logical net, it’s possible to pinpoint the physical x and y locations and layer information of where the defect is likely to be on that net with greater accuracy.

Volume-diagnosis-based yield analysis is more efficient if the collection of diagnosis data is started early in the technology-development process and is automated to handle large volumes of data. All of the tester failures can then be logged and used to produce diagnosis results. Even in early production runs, this could create a database of thousands of diagnosis results. The next step is to apply statistical analysis to all of this data.

Statistical analysis is based on the results of diagnosing a large number of failing devices on many wafers or manufacturing lots. If many dies have a bridge defect in one specific location, for example, statistical analysis can show that—while the defects appear to be randomly distributed across the wafer—this particular defect only occurs in the center of the wafer. This analysis indicates that a systematic issue is occurring because of a manufacturing-process variation or sensitivity to a particular physical feature or layout pattern (see Figure 2).

Industrial Case Study
The following is an example of how an IC design benefited from using diagnosis-driven yield analysis. The target design of this case study was a 10-million-gate graphics-processor chip at the 90-nm technology node. The study focused on an excursion wafer with 209 defective dies on it. All of these dies had failed structural-logic testing during manufacturing test. Out of the 209 scan-test fails, diagnosis showed that just over half of the dies on the wafer exhibited a defect caused by an open-defect mechanism. Yield analysis further indicated that a dominant open mechanism caused the excursion.¹

The process went as follows:

• Inputs to the diagnosis process flow were the design netlist, test patterns, physical-layout information, and fail logs of the dies that failed logic test during production test.

• The volume logic diagnosis of the fail logs determined logical failing locations for all of the failing dies.

• The design layout information was used to extract layout features that were likely to lead to interconnect opens when defective. Layout-aware extraction is a pre-processing step. After the features are stored in a database, the extraction doesn’t need to be repeated for subsequent analysis of that specific design.

• The two sets of information—diagnosis results and layout features—were analyzed together to determine the dominant open-defect mechanism within the set of failing dies.

• The root cause of the yield excursion was determined to most likely be an abnormality in a process step related to the fabrication of single vias in layer 2. Figure 3 shows a picture of the defective via.

To validate that single vias on layer 2(v2) were indeed the dominant failing feature in the defective dies, eight failing dies were selected for performing detailed physical failure analysis (PFA) of the defects. These dies were selected using diagnosis results from wafer probe testing.

The physical failure analysis of all eight selected dies isolated the defect to a malformed layer-2 via that was leading to an open net in the devices. The PFA then validated the diagnosis results based on the test failures caught on the tester. A metal deposition step in the manufacturing process was cleaned up, which resulted in improved yield.

Finding the root cause of the IC failures caught in manufacturing test can be a daunting task. It can take many days or weeks of failure-analysis time. To improve initial yield levels more quickly or increase mature yield levels, diagnosis-driven yield-analysis techniques provide a faster and more cost-effective alternative to traditional approaches. By using automated diagnostic techniques to zero-in on the defect suspect types and locations, the failure-analysis process is given a great head-start. It can therefore be completed more quickly. This change in the yield-analysis process significantly speeds the discovery and verification of the root cause of yield-limiting defects.

Another essential part of the yield-improvement methodology is to apply statistical analysis to volume diagnosis results. This process, which is especially important for smaller technology nodes, can help to separate random defects from systematic defects. Once systematic yield-limiting defects are identified, process improvements can be made to eliminate them and thus drive yield levels and profitability higher.

Reference:
¹. Sharma, M. et al., “Efficiently Managing Yield Excursions by Identifying Physical Root Cause from Test Fail Data,” presented at the 2008 International Test Conference.