To meet the overall power demands of the electronics market today, semiconductor designers and architects need to step up and deliver systems and chips that are leaner, meaner and greener. By "leaner," I mean that these devices need to be as small in form as possible. By "meaner" I'm referring to overall best performance. And "greener," of course, translates to lower overall power consumption.

This may all sound good, but how do we pull this off when system-level complexities continue to push design teams to the limit? The industry is moving towards smaller geometries, but with more capacity, and faster performance. But, what is being done to reduce power consumption? The burden is shifted to architects and designers. Since area, performance, power and chip schedule are inversely affecting each other, achieving balance is a challenge In order for design teams to be successful they must make power estimation a top priority and stay on schedule.

Power Analysis and Productivity: Oxymoron?

Current power analysis techniques are plagued with problems, most notably, productivity limitations. Chip architects need fast and productive ways to estimate power early. In most cases, ball park power estimation is sufficient, but seldom available. As engineers take a deeper look at the power, more accuracy is needed to sign off on a chip/system but accuracy is either sacrificed or it comes at a loss of productivity.

A common approach to high-level power estimation involves conducting spreadsheet-based analysis that draws on knowledge gained from past projects. Designers also tend to rely on software simulation at the gate level even though they are not getting performance they would need.

New projects are typically over 10 Mgates and with 4 or more cores. Even with a modest design, running at 100 MHz for 5 seconds real-time, that equates to duration of 500 million cycles, assuming one can run a simulator at a speed of about 100 Hz. It can take over a week to complete the test, so how can the project be completed on time?

Power Analysis — With Only a Microscopic View

Power analysis performed with traditional simulation captures a narrow window, for short tests and at the block level (Figure 1). Based on this, how can one ensure the power estimation is within the allocated power budget? If this is unknown, how can you work around Under Spec issue, and what is the appropriate margin?

Figure1: Power analysis using simulation; a microscopic view

If you want to do system-level analysis, the productivity problem only gets worse with current approaches. Many designers tend to cut corners by settling mostly block-level simulation instead of full chip or system power estimation and analysis. How do you get the level of accuracy desired at various phases of the design with high productivity?

Architectural decisions and stimulus applied to the design have a lot to do with the power consumption and can not be ignored. If you overlook full system-level analysis, it's a huge risk.

Inaccurate Power Analysis Introduces Risk

When engineers make decisions about average and peak power dissipations from the block-level tests, they often "over spec" their system power budget; that is, they select the most conservative estimations possible, so the margin for error tends to fall on the side of lesser consumption rather than more. This in turn can have ripple effects on the entire design, ultimately resulting in packaging and cooling requirements that add significant cost to the final product. While expensive packaging and cooling may reduce the chance of chip failure in the field, better power estimation can achieve the same result at a lower cost, allowing for superior products.

If average and peak power is measured higher than expected, the situation is reversed, and the device is considered "under spec'd." In this situation, potential problems include poor battery life, reduced reliability, and in some of the worst cases, delayed time to market or even financially debilitating product recalls.

Chips designed with low power in mind that require a desired feature set in a small area with adequate performance can have a significant advantage over competing designs. One way to achieve this is by running "deep" cycles to analyze and make proper trade-offs between power consumed and performance.

What's the Solution?

The ideal solution would deliver the following:

• Superior productivity: A high-performing, automated approach to system-level analysis enabling designers to run real application tests. An ability to run hardware/software 'what-if' scenarios and adjust the design mid-stream without harsh consequences to the overall schedule.

• Increased predictability: Support the ability to measure power during various design phases, including the ability to measure IP and various architectural options and when to run application tests.

• Reduced risk-cost compromise: Adequate accuracy of average and peak power at various design phases to make sure the design stays within allocated budget, allowing design teams to run realistic scenarios and make well-informed decisions regarding power management strategies, IP selection and packaging and cooling technologies.

Cadence recognized these system-level challenges early on and embarked on the Power Forward Initiative. These challenges are now addressed by leveraging the high-performance Palladium III engine and RTL compiler power estimation capabilities in Palladium Dynamic Power Analysis – a part of the Cadence Low-Power Solution offering.

Dynamic Power Analysis — With Telescopic and Microscopic Views

Cadence Incisive Palladium Dynamic Power Analysis offers the ability to intelligently identify true peaks and average power based on switching activity in complex SoC designs and offers analysis capabilities through automation.

Dynamic Power Analysis is used within an emulation flow using RTL or gates with technology libraries to analyze power consumption when using applications software. Optionally, with the Cadence C-to-Silicon Compiler, you can also take C or SystemC models and produce RTL or gates to perform early power analysis.

Figure 2. A global (Telescopic view) and a detailed (Microscopic view) using Palladium III Dynamic Power Analysis.

First, a coarse-grained (take samples every few cycles) analysis is done to get a global view. Then users select the window of interest, and then fine-grained (cycle accurate) analysis is performed.

Dynamic Power Analysis uses a patented master and slave file approach to reduce file size with the ability to better process the data in parallel so the entire process can be managed effectively. The GUI provides a power profile report file, and hierarchical view. In addition, data processing and filtering capabilities can be useful to isolate the area where detailed analysis is needed.

Practical Power Profiling for Whole Chip or Block

Palladium's Dynamic Power Analysis allows you to profile the whole chip or zoom in on a block to correlate performance-sensitive functions to power consumption to ensure quality of service. It also helps identify power consumption at the instance level, block level or for the entire chip.

Figure 3: Power profiling: whole chip and zooming to block.

Early results are showing a high degree of correlation with simulation-based results. In addition, the results are also very close to silicon when using post-layout netlists with the standard parasitic extraction format (SPEF) for the same tests under same conditions. Dynamic Power Analysis is unique in its ability to create a power profile while running software that can run for several hundred million cycles.

Conclusion

Engineering teams are discovering a greater need to analyze and verify power and performance tradeoffs at the system level. Cadence now delivers a Dynamic Power Analysis solution as a part of the Cadence Low-Power Solution to address system-level power estimation and analysis. Dynamic Power Analysis provides the necessary measurements at the architectural, design and implementation levels, enabling a successive refinement approach. The automated flow and ability to run long, real scenarios and correlate power with performance are essential to power budgeting, package selection and overall risk and cost reduction strategies.

Dynamic Power Analysis is a pioneering product that enables architects and designers to keep up with the ever increasing demands of balancing performance and power in an applications-hungry world. It provides a compelling bridge between the chip and software design worlds, ensuring that engineers in both disciplines can communicate and take advantage of advanced power management technologies.

Notes:

• Average power is used to determine packaging and cooling decisions. It also reveals the battery life of the device. The average is calculated by factoring in multiple states/uses of the device. For instance, in the case of a mobile phone, idle, talking, and listening and Internet usage time, etc. modes are all considered. Better average power depends on the most appropriate use modes (test stimulus) and longer test lengths under real-life scenarios.

• Peak power provides a better measure for determining if a device will fail. Typically, the user is concerned about maximum peak that could occur and existing package/layout is inadequate to support the peak power. To determine peak power needs, system-level tests needs to be run and scanned for maximum switching/current draw. Max peak may be millions of clocks away, which can be missed by simulation alone.

Acknowledgements

The author would like to thank Yong Fu and Edward Musall for their contributions to this article.