With the persistently grim news on the economy, we're all learning to do more with less. This is especially apparent within the semiconductor industry as companies reassess their business plans and budget to do more with less ... much less, in fact. In many of these companies, the need to do more with less, combined with sheer design size and complexity, is helping to drive hardware emulation into the favored slot as their most popular verification tool.
Setting aside our economic woes, let's focus on verification. Over time, it has gotten more expensive no matter how many resources are assigned to it and it consumes a large portion of the development cycle. More and more, a low-cost, high-performance emulation system is becoming a well-used component of a hardware/software co-design flow.
As companies move to system-on-chip (SoC) designs, the need for emulation has never been more acute. Their economic worries are compounded by the increased concern of how to debug the embedded portion of the system. They've struggled with how to find a software bug that showed up in hardware or a hardware bug that showed up in software.
Hardware emulation provides an all-in-one system for hardware debugging and embedded software validation. With emulation, hardware designers and software developers share the same system and design representations and work together to debug hardware/software interactions. However, to be effective, the emulation system must have a software-aware debugging environment that tracks a bug in hardware coming from the software debugger. This is especially attractive when the mantra is do more with less.
Traditional emulation systems don't suffice because they execute at sub-megahertz speeds — unacceptable for software developers –— and do not have the software-aware debugging environment — unacceptable to hardware designers. Rapid prototyping systems are fast but have limited debugging means and no software-aware debugging environment either, hence unacceptable to hardware designers.
Performance and price have always been important considerations when selecting an emulation platform, and these features are even more important in today's austere times. Many of the commercially available verification products and solutions do not address complexity or performance and cannot be used when developing embedded software.
Field programmable gate array ( FPGA)-based emulators are more reasonably priced than those based on custom chips and have been able to shorten the overall verification cycle of complex chip and electronic systems designs. Older generations of emulation systems have largely been replaced because of their complexity, high cost and poor performance.
In this economy, design teams are turning to hardware emulation as a preferred tool to a hardware/software co-design flow due to its desirable price, performance and flexibility and doing more with less.
Lauro Rizzatti, general manager of EVE-USA, has more than 30 years of experience in EDA and ATE, where he held responsibilities in top management, product marketing, technical marketing, and engineering. Lauro can be contacted at firstname.lastname@example.org.
Are you up-to-date on important SoC and IP design trends, analysis and market forecasts?
Chip Design now offers customized market research services.
For more information contact Karen Popp at +1 415-305-5557
Santa Clara, CA January 27-30, 2015
San Francisco, CA February 22-26, 2015
San Jose, CA March 2-5, 2015
Grenoble, France March 9-13, 2015
Mesa, Arizona March 15-18, 2015
Santa Clara, CA May 6-7, 2015
Encore at the Wynn Las Vegas, NV May 19-22, 2015