Synopsys is beefing up its Discovery verification platform, a move that is at the forefront of a projected recovery in the electronics industry and a new push for tools that can help ease the burden of increasingly complex SoC designs.

Key to Synopsys’ rollout - and one that also is front and center in new tools from rivals Mentor Graphics and Cadence - is the ability to both use multicore versions of the tools to speed up things like simulation and verification, as well as the ability to use those tools to design more multicore chips. While this may sound a bit like the dog chasing its own tail, the reality of chip design beyond 65nm is that almost all chips will include multiple cores and many will include more functionality - some of that analog.

A second challenge is that all will include an increasing amount of power management within the design, which means complexity will increase by orders of magnitude as chips are built with multiple power islands, voltage changes both up and down, software to manage performance in a chips multiple cores, as well as the various modes of on, off and sleep.

One of Synopsys’ key innovations is a multicore version of its VCS functional verification toolset. "What we’ve done is add more resources," said Steve Smith, senior director of platform marketing at Synopsys. "This allows you to increase the number of computers used to verify a design."

At the same time, VCS allows you to write assertions in System Verilog and "parallelize activity to run on multicore," Smith said, who noted that the tools will work for both homogeneous and heterogeneous cores. That agnostic approach is important for being able to use the tools to serve homogenous chips made by companies like Intel and Freescale, as well as those design for specific purposes by most other companies.

Mentor Graphics announced a similar direction with its Calibre verification platform and its Olympus place and route tools and Cadence has done the same with Encounter. Whose solutions prove to be the best in these areas ultimately will be answered by the engineers who use them.

Synopsys also introduced a multicore version of its CustomSim circuit simulation for analog and mixed-signal circuits, which is also part of the Discovery platform. "What we’ve found is that customers need to run more accurate simulation at the SPICE level," said Geoffrey Ying, director of product marketing for Synopsys’ mixed-signal simulation products. "There are more process corners to deal with and chips are becoming much more complex in size and physical effects at sub-90nm. An SoC now has numerous different functions, such as embedded memory and digitally assisted analog, and they’re all being integrated onto one chip."

CustomSim adds assertions for analog circuits, support for level shifters and native circuit checks. "It’s difficult to check that right now if a vector doesn’t cover that," Ying said.