Published in April / May 2009 issue of Chip Design Magazine
A global demand for low-power semiconductors has been created by the tremendous growth in battery-operated and power-sensitive applications—not to mention the fast-rising design-for-energy-efficiency dynamic. Indeed, low power is currently one of the industry’s driving factors. It’s putting enormous pressure on system engineers, who face stricter design specifications and standards that cap total system power consumption. A few extra milliwatts or even microwatts can add up to a major power-budget headache for a portable-device designer. At the same time, demand continues unabated for more features, performance, and flexibility. These needs must be met without draining the battery or increasing costs. Managing these design tradeoffs has become a paramount concern for today’s system engineers in every discipline ranging from mobile phones to medical equipment (see sidebar, “Tips to Minimize Power Consumption when Designing with FPGAs”).
To meet their low-power constraints, designers have relied on application-specific integrated circuits (ASICs) rather than field-programmable gate arrays (FPGAs). But ASICs can hamstring engineers. Their use translates into longer time to market, hefty non-recurring engineering charges (NREs), and a lack of flexibility to address changing standards and late-stage design modifications. Thus, hard-wired ASICs are riskier and often impractical for applications with short product life cycles.
Similarly, the complex programmable-logic devices (CPLDs) used in some low-power applications are losing their effectiveness because of relatively high costs and the increased demand for high-end features and extra logic. CPLDs don’t offer the level of integration, flexibility, or sophistication required for most of today’s applications.
Enter FPGAs. More and more, designers are looking for a low-power, reprogrammable solution that will let them adapt to evolving standards, speed time to market, and deliver the footprint and power consumption required. According to market-research firm iSuppli, this shifting interest is so keen that as much as $3 billion of the estimated $20-billion ASIC market could potentially shift to low-power FPGA solutions in the coming years.
Not all programmable logic is suited to address low-power needs, however. FPGAs based on static-random-access-memory (SRAM) technology have inherently high static power consumption. Even “low-power” SRAM-based FPGAs draw on the order of 10X more power than what’s specified for typical battery-operated applications. Some of these “low-power” FPGAs draw upward of 30 mA, which is often an order of magnitude or two higher than what can be tolerated by typical power-sensitive, battery-operated applications. At startup, SRAM-based devices experience well-documented in-rush and boot-up configuration power spikes during system initialization. These power spikes can cause excess battery drain and failures.
Once the FPGA is on and configured, power consumption takes two basic forms: static and dynamic (also called active). Static power consumption is the current drawn by an FPGA when it’s powered up, configured, and doing nothing. In contrast, dynamic power is consumed when devices are actively working. Until recently, dynamic power was the dominant source of power consumption. Once helping to manage the dynamic power problem, device supply voltages (Vcc) had dropped with process shrinks and subsequent lower system voltages.
Figure 1: Static Power becomes significant at 90 nm.
The days of continued scaling are gone, however. Compounding the issue, each process-node shrink means additional static power consumption for transistor-heavy SRAM-based FPGAs (see Figure 1). This issue arises from worsening problems, such as quantum tunneling and sub-threshold leakage, which create real challenges for the devices targeting power-conscious applications. With leakage worsening, static power is becoming the designer’s biggest concern (see the Chart).
By contrast, where the SRAM cell structure incurs substantial leakage and requires power-consuming configuration memory, Flash-based cells have no leakage path. As a result, they have 1000X lower leakage per cell than SRAM. And a Flash-based solution can offer up to 16X better power per I/O. Assuming a design requires 100 I/Os, a 120-I/O device can consume as little as 5 µW versus the roughly 60 µW of competitive solutions.
To address some of these power concerns, several suppliers of SRAM-based FPGAs claim to offer “single-chip, Flash-based” solutions. These “hybrid” solutions merely combine Flash-memory components with the underlying SRAM FPGA technology, which is either integrated with the FPGA die into a single package or—alternatively—stacked or placed side by side. Unfortunately, the FPGA array is still volatile and is subject to the power drawbacks associated with these types of devices. With such solutions, the embedded Flash-memory blocks control only the initial configuration of the devices during power-up.
Certainly, both the silicon-in-package (SiP) and the multichip-package (MCP) hybrid approaches overcome some of the limitations of traditional SRAM-based solutions. They provide a smaller footprint, a minor reduction in power consumption, and small advances in power-up time and security. But these are only incremental improvements over their pure SRAM-based peers.
The Flash-Based FPGA Solution
Single-chip, Flash-based FPGAs help to solve the low-power problem. They don’t require an external configuration device (i.e., boot prom or microcontroller) to support device programming at every power-up cycle. A live-at-power-up feature eliminates the need for an external device to assist in system power up. In addition, removing the additional parts required by SRAM-based FPGAs reduces board space and system power consumption. It also increases reliability, simplifies inventory management, and lowers total system costs by as much as 70% compared with similar SRAM-based FPGA solutions.
As complete Flash-based solutions, these devices are augmented by software that enables power-conscious design including power-driven “layout” and advanced power-analysis capabilities. It therefore allows users to minimize the power consumption of their systems. Each watt that’s conserved reduces system operating costs. As a result, the deployment of cost-effective power-management solutions at the enterprise level saves huge amounts of money as well as energy while generating significant environmental benefits.
High-density Flash FPGAs can deliver up to 1700X less static power when compared to high-density SRAM FPGAs. When compared to low-density FPGAs and CPLDs, Flash FPGAs can deliver up to 25X lower power.
Design For Reality
For an example of how this works in practice, take a look at the medical-device sector. Here, increasing emphasis is being placed on new and advanced technologies for prevention, early diagnosis, and treatment. Pressures to reduce healthcare costs are butting into the demand for more portable devices, which—when deployed in the home, doctors’ offices, and elsewhere—can save money for the healthcare system. Portable medical equipment made big news at the 2008 Beijing Olympics, when companies like GE were test driving portable MRIs and other imaging and diagnostic tools.
For wide deployment, these devices need to be low power, flexible, and cost effective. FPGAs—with core voltages down to 1.2 V—play a big part in this development. They allow the programming of various features and the design for differing geographical standards while keeping power low and design costs down.
Today, medical devices—for example, digital blood-pressure, blood-gas, and blood-glucose meters—must be robust as well as ubiquitous. They’re expected to do much more than just testing and monitoring. Some are now capable of logging and analyzing data as well as communicating accurate results to the healthcare provider. Blood-pressure meters are now benefiting from a more extensive data-logging feature as well as communication ports for real-time sharing of information with the healthcare provider. Insulin meters are equipped with communication ports (IR/wireless) to transfer real-time measurements to the PC or insulin pump in order to treat the disease. In their most basic form, these portable medical devices are all battery-operated, micro-controlled handheld devices with power constraints.
In Figure 2, the blocks represented with white outlines represent some possible functions that can be implemented in FPGA devices. These functions can be individually addressed as needed by smaller, low-power reprogrammable FPGA devices or integrated into larger FPGA devices. These ultra-low-power FPGA families offer gate capacity from 10 kgates to 3 million gates.
Figure 2: The Patient Monitor Block Diagram shows blocks that can be implemented in FPGA devices.
Typically, the insulin pump is controlled by a microprocessor. These microprocessors perform various functions, such as processing data from bio-sensors, storing measurements, and analyzing results. Gone are the days when the design tradeoff necessitated the use of a slow, mopey MPU. Today, low-power designs can take advantage of full-featured processors, such as an FPGA-optimized, 32-bit ARM Cortex-M1.
Implementing MPU or controller features in a low-power FPGA is just one aspect of evolving portable-medical-device design, however. One of the most important and potentially power-hungry features is the display. Lower costs and ease of mass manufacturing have increased liquid-crystal-display (LCD) panel demand in various home-based and commercial medical markets. When creating these devices to meet consumer demands (reference the simple LCD-controller block diagram), designers select LCD panels based on critical factors like size, resolution, reliability, power consumption, and product life cycle.
Because newer displays with enhanced capabilities and features are continuously being launched, designers must keep up with technology by redesigning the display controller. This costly task can significantly increase time to market. Designers therefore need solutions that will enable them to incorporate the latest technology with minimal cost and effort. Ultra-low-power and reprogrammable FPGAs provide solutions to address these challenges.
For three decades, FPGAs have carved out a profitable niche as customizable devices that give designers a choice over ASICs—especially when they want to get to market quickly in low volumes. Until now, engineers who wanted to choose FPGAs for power-sensitive designs found themselves in a bind. Flash-based FPGAs have now emerged as a low-power alternative to SRAM-based FPGAs. In addition, they’re challenging the once-inviolable differentiator of ASICs and CPLDs: low power. In an era when more devices are mobile and require long battery life or when energy efficiency needs to be designed into new systems, FPGAs are emerging as a fast, flexible, and affordable low-power alternative to ASICs and CPLDs.