When evaluating IP attributes, IP integrators consider several parameters including cost, testability, availability of proven silicon, level of support and performance. However, one important consideration is often either ignored or assigned a low level of importance – portability between silicon foundries at the same process node. This is unfortunate, since maximizing IP reusability goes beyond reuse of that IP in different chips. Designers must also consider IP reuse at the same process node but at different foundries, particularly important for third-party IP providers, as well as potential future migration of the IP to other process nodes.
All silicon foundries that support a particular process node are not alike in the way that they implement silicon at that node. While many chip-processing operations are pretty much the same from foundry to foundry, each implementation process has its own distinct set of design rules and process variations that the foundry uses to optimize chip performance. These differences make it difficult for a chip or a silicon IP company to develop products targeting multiple foundries. Even with relatively non-complex IP, silicon proven at a particular process node at one foundry may have significant problems when implemented at the same process node at a different foundry due to seemingly minor process variations.
The ability to support different foundries is important for chip vendors who may not want to depend on only one silicon source as well as for third-party IP vendors since different customers will have different foundry requirements. For the IP vendor, ease in redesigning and qualifying IP at multiple foundries translates to better support of the IP integrators who are not locked into a single foundry. Similarly, process scalability for an IP developer allows the IP integrator to reduce chip cost or enhance its performance.
Designing IP for Portability
If you want to maximize the foundry portability of silicon IP, you need to minimize that IP’s performance dependence on the individual process steps that are unique to a particular foundry. This reduces the complexity of redesigning IP for processing at different foundries. It also simplifies IP redesign for implementation at smaller process nodes.
The following example of an antifuse-based one-time programmable (OTP) bit-cell demonstrates how differences in bit-cell architecture can strongly affect the process portability of OTP memory arrays. The following discusses a two-transistor (2T) vs. one-transistor (1T) antifuse bit-cell, both implemented in a standard bulk CMOS process. For both devices, the bit-cell is programmed by putting a sufficiently high programming voltage (PGM) on the thin oxide transistor’s gate, breaking down the oxide and forming a permanent link between the gate and the channel, which represents a programmed state.
A 2T bit-cell is shown in the following figure.
One of the problems with the 2T bit-cell architecture is that oxide breakdown during programming can occur in one of three regions: from gate-to-channel; from the gate to the leakage control implementation, sometimes called a Halo implant; or from the gate to the LDD region, which is used to control drain-substrate breakdown.
With three distinct breakdown regions, the 2T bit-cell architecture exhibits a multi-model current distribution in the programmed cells. This reduces OTP reliability and increases programming complexity. Since Halo and LDD process steps are foundry dependent, retargeting 2T-based antifuse OTP memories for different foundries and then qualifying that IP for those foundries can be difficult and time consuming.
A 1T bit-cell such as Sidense’s 1T-Fuse™ Split-Channel bit-cell, shown in the following figure, minimizes memory IP dependence on foundry-specific process “tweaks.”
Since are no LDD regions or halo implants at the edges of the thin oxide, the breakdown region is confined to the channel below the thin oxide and exhibits very consistent characteristics from bit cell to bit cell in a memory array. This simplifies the task of porting memory IP based on the 1T Split Channel architecture from foundry to foundry and, inherently, makes memory IP comprising arrays of these bit cells more easily scalable to advanced process nodes.
Developing IP to be “foundry friendly” requires more design resources and extra time, but is worth the effort. IP that is easily ported between foundries saves time and money, enhances reliability, and reduces product risk. IP designed in this way has greater IP integrator appeal and will definitely result in superior reusability in and higher profit margins for the chips in which that IP is used.
Jim Lipman is Director of Marketing at memory IP provider Sidense. Prior to Sidense, Jim received his BSEE and MSEE degrees from Carnegie-Mellon University in Pittsburgh and his Doctorate in Electrical Engineering from Southern Methodist University in Dallas. He also has a Masters of Business Administration from Golden Gate University in San Francisco. Jim is a senior member of the IEEE.
Are you up-to-date on important SoC and IP design trends, analysis and market forecasts?
Chip Design now offers customized market research services.
For more information contact Jenna Johnson at 612.598.3446