Next Step: Full-Chip SynthesisMentor rolls out enhancements to Catapult C for control logic; race is on to integrate more pieces across system-level design.
This is a full-flow problem, from the earliest architectural conception to the final debugging and verification that all components work individually, together and at various power levels.
All of the major EDA vendors have been attempting to tackle this problem, with varying degrees of success. The newest entry on this subject is Mentor Graphics’ introduction of control logic into its Catapult C Synthesis tool, in addition to low-power management.
Mentor has been making acquisitions in this direction for several years. It acquired Agility Design Solutions’ C Synthesis assets in January. It also bought Summit design in 2006, which makes ESL tools. But it also has been doing some heavy duty investing of its own in high-level synthesis.
"The goal is full-chip synthesis," said Shawn McCloud, product line director for high-level synthesis at Mentor. "We started in the wireless space with this and expanded into video. The culmination of all of this work is in control synthesis."
There are actually three kinds of control logic - intra-block control, multi-block dataflow control and the new addition to this mix, reactive inter-block control. The latter is the newest development. It is explicitly defined in the C++ source code, its primary function is control rather than processing.
The entire design can be modeled in C++ now, including algorithm, structure and control, which can be used to automatically generate RTL for control blocks. That alone helps solve some integration issues.
"What happened when we moved from assembly (language) to C++ is designers lost some control," said Simon Bloch, vice president and general manager of Mentor’s ESL and HDL Design and Synthesis Division. "Today they need both algorithms and control. What we’ve done is put C++ and assembly into one approach."
The final piece is low-power optimization, which both Mentor and Synopsys have been racing to solve. In Mentor’s case, that includes automatic multi-level clock gating for dynamic power, fine-grain optimization and dynamic clock and voltage management. Being able to use technology for this kind of function, rather than trying to do it by hand, was convenient at older process nodes, but it is almost impossible to figure all of this out by hand at advanced process nodes with multiple power islands, cores and voltages.