Productivity Soars With New ProofGrid Technology
MOUNTAIN VIEW, Calif. --(Business Wire)-- Jul 13, 2009 Jasper Design Automation, provider of advanced formal technology solutions, announces its latest product, JasperCore™. JasperCore harnesses the proven capabilities of the company’s formal analysis engines to boost productivity and decrease the cost of deployment by performing numerous parallel runs using ProofGrid™, a new capability that distributes formal technology. Together, JasperCore and ProofGrid allow users to implement multiple proofs, tasks, and applications, across multiple cores and computers, efficiently serving multiple users, even across multiple business units.
ProofGrid, presently included in both JasperCore and JasperGold® (the company’s flagship formal verification tool), enables this through the dynamic allocation of properties, proof engines and licenses over a computer network for parallelism and efficiency. ProofGrid significantly raises formal verification throughput and performance by leveraging the emerging power of local machine, cluster, and computer farms. It also provides seamless and powerful distribution and collaboration management for proof engines running on the network under a unified tracking console. The result is soaring productivity as users are freed from manually separating and dispatching multiple, single runs and then collecting the results for each.
As part of this major new product release, both JasperGold and JasperCore have been re-architected to include even more proof power, with more verification performance and capacity, and reduced memory and processing requirements. Significant enhancements include faster proof and visualization flows, proof engine enhancements, and high-performance design-traversal or “smart” algorithms to speed debugging. Powerful abstractions such as new Proof Accelerators and Scoreboard increase the power, capacity and performance of the tools. Proof Accelerators are formal modeling methods that significantly reduce the state-space of a design through optimized modeling (abstraction) of common design functions.
In addition, JasperGold now incorporates QuietTrace™, a new feature shared by Jasper’s design and reuse solution, ActiveDesign™. QuietTrace is a visualization and debugging capability for RTL development that reduces iterations by allowing the user to focus only on the most relevant issues impacting the design.
QuietTrace works with Jasper’s Visualize™, which automatically generates and manipulates waveforms without a testbench, answering “what-if” design questions and providing visual confirmation of design functionality which is especially useful for RTL development and debug. Visualize in JasperGold lets designers use formal technology more easily and efficiently, without assertions. In ActiveDesign, Visualize pairs with Behavioral Indexing™ (for the extraction, indexing and storage of design behaviors in a database) to create an executable specification of the design to promote design understanding, knowledge transfer, and leverage.
Another important addition to ActiveDesign is Implication Analysis™, technology to extract and compare structural information on multiple revisions of the RTL, and behavioral analysis technology to extract and compare waveforms generated from recipes on multiple revisions of the RTL. Used in combination with Visualize, this analysis highlights the effect of design changes by displaying precise differences in behaviors.
JasperCore is now available, as are the newest, updated versions of JasperGold and ActiveDesign. For more information and pricing, contact Jasper at: info @ jasper-da.com.
Jasper At DAC 2009
JasperCore, JasperGold and ActiveDesign will all be featured at Jasper’s DAC Booth 3767. For more information, or to register for a product demo during the show, visit: http://www.jasper-da.com/dac/dacreg.htm.
About Jasper Design Automation
Jasper delivers industry-leading EDA software solutions for semiconductor design, verification, and reuse, based on the state-of-the-art formal technology. Customers include worldwide leaders in wireless, consumer, computing, and networking electronics, with over 100 successful chip deployments. Jasper, headquartered in Mountain View, California, is privately held, with offices and distributors in North America, South America, Europe, and Japan. Visit www.jasper-da.com for Targeted ROI: reducing risks; increasing design, verification and reuse productivity; and accelerating time to market.
Are you up-to-date on important SoC and IP design trends, analysis and market forecasts?
Chip Design now offers customized market research services.
For more information contact Jenna Johnson at 612.598.3446