Published on August 17th, 2009
To get the most out of process technologies coming on line right now, designers need to radically re-think their strategies for timing closure. The additional burdens of accounting for process variability, managing leakage and hitting a low power budget make obtaining market leading performance extremely difficult.
To overcome these increasing burdens, designers and their managers have to reduce margins that exist within timing models provided by a 3rd party IP provider or a central library group. This will require designers to take control of how library views are created to better tune their models to suit their specific design goals. The best way to do so is to characterize the libraries.
Today, designers working on actual production designs for 65, 45 and 40 nm processes are left with no window to work with – and the situation will only get worse as we head toward 28 and 22 nm. For example, timing signoff can be achieved at the worst case corner at high temperature but not at low temperature. The impact of variation and temperature inversion is greater for lower voltages; yet these are now the norm due to the need to reduce power. The irony is that the overlying process technology can often easily deliver on the design goals but the tools, models and methodology get in the way. Every tool and every modeling level adds margin until all the guard bands eat up all the design space
Areas that need careful consideration are, among others: 1) how the pin capacitance is measured; 2) what type of pre-driver was used; and 3) how is setup and hold measured for flip-flops, latches and on- clock gating cells.
By characterizing libraries, users can get a wide range of choices for how simulation data is captured, measured and margined before it is encapsulated in Liberty™ format. For example, the value of pin capacitance varies by up to 50% depending on the measurement thresholds and this can have a major impact on hold time closure. For setup and hold values, there is often additional margin added by the IP provider to avoid warnings from downstream tools. For example, certain tools do not support negative setup or hold times so margin is added to the library to remove the negative constraints.
For designs that use multiple voltages and/or dynamic voltage scaling, if the library views do not explicitly cover the voltage being used, the delay calculator will use interpolation which is nearly always pessimistic. By characterizing more voltage corners, higher accuracy can be achieved reducing built-in margins. In addition, by the time the library is delivered the process models used to create it may have changed. Typically process models tighten their margins as they mature, but if the library isn’t up to date, then the timing closure tools will not enjoy this benefit and will continue to over-margin. For memory IP blocks, the timing and power models are created by a compiler without knowing the exact context of how the memory block will be used. The compiler creates the model for each instance from fitting data derived from the characterization of a small set of memory instances. A more accurate model without additional margin can be achieved by characterizing the exact size for each instance of each memory block using the exact loading, slew rates, voltage and temperature values for each design.
The investment required to do project or design family specific characterization is relatively small. A new library corner for even a thousand cells can now be completed in half a day or less using a single eight core machine. Smart characterization engines now exist that can automatically setup and optimize the characterization directly from analyzing the transistors inside the cell. This also allows design teams to take control of the library delivery schedule so they do not need to rely on the over-burdened central group or to pay additional fees if a new corner, or different characterization setting is required.
Margins are necessary to help safe guard against inaccuracies inherent in abstracting silicon components to the higher models. However, over guard-banding is creating a huge barrier to the effective use of 65nm and below process technologies. While using statistical methods will greatly help by providing a more realistic timing answer taking control of the margins inherent in off the shelf IP models can also alleviate many timing closure challenges. To accelerate their schedules, designers should start their own characterization engines.
Prior to Altos, Jim was the Timing and Signal Integrity Marketing Group Director at Cadence. He was the VP of Marketing and Business Development at CadMOS when they were acquired by Cadence in 2001. Before CadMOS, Jim was Executive VP at Ultima Interconnect Technology (which as Celestry was acquired by Cadence in 2003), Major Account Technical Program Account Manager at EPIC Design Technology (which IPO'ed in 1994) and a Member of Group Technical Staff at Texas Instruments. Jim holds a BS in Math/Computer Science from Manchester, UK and has over 25 years experience in EDA.