This is a virtual roundtable discussion on structured ASICs-the product offerings and the issues related to the technologies available today. The impetus for this discussion is the growing amount of noise being directed at these new (or possibly not-so-new) technologies. As process dimensions shrink, not only do the costs for mask sets increase at a rate inversely proportional to process geometries, but the costs of design in time and manpower begin to exceed any possible return on investment other than that for the very highest volume products.

Among the alternatives to standard cell ASICs are various flavors of FPGAs, and a new category of products called structured ASICs. These products are trying to address the growing gap between the standard cell designs used for high-volume, high-performance or low-power designs versus the rest of today’s designs, the ones that run in volumes of 250,000 units or less.

The participants in this discussion include the following spokespeople and their companies. Barry Marsh, vice president of product marketing, Actel Corp. (Mountain View, CA); Peter Woo, director HardCopy product marketing, Altera Corp. (San Jose, CA); Vince Hopkin, vice president for structured digital products, AMI Semiconductor, Inc. (Pocatello, ID); Jay Johnson, marketing director, ASIC/ASSP business unit, Atmel Corp. (San Jose, CA); Ze’ev Wurman, vice president for software, eASIC Corp. (San Jose, CA); Martice Chen, Vice President, Marketing and Operation, Faraday Technology Corp. (Sunnyvale, CA); Chung Ho, director, custom LSI strategic business unit, NEC Electronics America, Inc. (Santa Clara, CA); John Gallagher, director of ASIC synthesis marketing, Synplicity, Inc. (Sunnyvale, CA); Richard Tobias, vice president, ASIC & foundry business unit, Toshiba America Electronic Components, Inc. (Milpitas, CA); Max Lloyd, CEO, ViASIC Inc. (Durham, NC); and Chuck Tralka, director of product marketing, advanced products group, Xilinx, Inc. (San Jose, CA).

The participants submitted their answers to the questions electronically.

Barry Marsh, vice president, Product MarketingActel, Corp.

Off to an important start

The first question to the group was to define a structured ASIC.

Hopkin of AMI started off by saying that a structured ASIC is an integrated circuit (IC) architecture and methodology that delivers reduced entry cost and faster time-to-silicon using a predefined arrangement of late-stage, mask-customizable logic and pre-designed and pre-diffused macros and IP.

Most of the others said something along the same lines, except for Tobias at Toshiba who noted that Gartner/Dataquest believes the term “structured ASIC� is too narrow, and prefers to define the emerging market as “platform ASICs.� Gartner defines platform ASICs as “products in which close to half the chip is pre-determined and pre-verified by using pre-defined intellectual property (IP) that is embedded in the device, and the customer customizes a portion of the device,� and they identify three distinct types.

The first structured ASIC category is an “array-based platform� where IP is embedded in the wafer, and the customer customizes a portion of the chip with only the final metal layers. The second category is the cell-based-with-PLD-core platform, and the third category is the cell-based platform. Toshiba agreed with these categories and said the term “structured ASIC� is too confining. Gartner/Dataquest’s term “cell-based platform� describes the category in which products from Toshiba and IBM fit.

Hopkin challenged Toshiba to describe how their offering differs from cell-based ASIC. He said, “I’m not seeing anything that would lead one to conclude that SoCMosaic is any different than traditional ASIC. For example, it would be ridiculous for Actel to argue that their anti-fuse FPGAs are structured ASICs because they are not SRAM-programmed. Obviously Actel is not saying this, but how is Toshiba’s offering different?�

Gallagher of Synplicity said structured ASICs differ from gate arrays in that the ASIC vendor has also embedded in the architecture a design methodology and flow. Things such as test, power and clock-grid design, and IP integration, which previously were implemented via tools, are now being implemented via the architecture. The tools for structured ASICs embed the architecture-another change from gate arrays. Tasks historically done by the ASIC vendor are now done in the tools-for instance, design-rule checking, handoff checks, and vendor-specific, “layout-friendly� assumptions for placement and routing.

Johnson of Atmel said, “I consider the newly named “structured� movement little more than a re-birth of gate arrays, and only slightly more complex, with pre-defined cores, memory and metal programmability. At Atmel, we’ve chosen not to call our ASIC products “structured.� Rather, we have given them the SiliconCITY brand name, which is a standard-cell “platform� approach where at least 50 percent of the chip design remains the same by using IP and architecturally validated ARM-core based standard products. We can turn first-time-right silicon on these designs in as little as 3 months with competitive NREs (non-recurring engineering costs) of less than $200,000.�

Johnson continued, “As for gate arrays-we still do a few of those, if it’s just gates and memory underlayers. It really all boils down to matching the right technology with customer’s need for success. The big question in my mind is whether there really is a technology gap or market, between the FPGAs and the custom cell-based designs that structured ASICs address?�

Peter Woo, director, HardCopy product marketing Altera, Corp.

What’s it worth to you?

The second question the panel addresses centered on the value proposition for structured ASICs. The question drew a wide variety of answers, most of which revolved around cost and time. After excising the predictable marketing claims, here are the various responses and rebuttals.

Marsh of Actel disparaged the structured ASIC concept for not being as fast as a standard-cell ASIC, nor as cheap on a unit basis due to the increased die area. He also said the technology is not significantly faster to market than a standard cell. Marsh felt that although fabrication time is supposedly shorter because fewer layers are required, in the real world where wafers wait in line to be processed, it’s not the number of metal layers, but the number of wafers ahead in the cue which determines final fabrication time.

Hopkin of AMI disagreed with Marsh: “Our hybrid processing approach specifically addresses this issue. We run all the programmable layer processing steps in our own fab, so we have full control over scheduling. We typically deliver prototypes 10 to14 days after tapeout. There’s no way a cell-based ASIC can compete with that turn around time.�

Woo of Altera felt that the value proposition for a structured ASIC is based on reducing the number of mask layers required, versus those required for a standard-cell ASIC, which in turn leads to lower NREs and faster turnaround manufacturing times. He added that Altera’s structured-ASIC approach provides some very specific benefits in addition to advantages in cost and time.

Woo said, “We provide the ability to verify the design in an FPGA and then move seamlessly to a pin-compatible structured ASIC manufactured on the exact same process as the FPGA. In terms of reducing concern for physical effects at layout, as an FPGA company this is something we have always been providing to our customers. Our business has always been about allowing customers to focus on functional design and letting our design software and chip architectures take care of the design implementation decisions. Our HardCopy offering takes it to the next level by providing the ability to do it with a structured ASIC.�

Hopkin of AMI noted that structured ASICs reduce design costs over a cell-based solution, both in physical design and in mask cost. He said they reduce time to silicon, over a cell-based solution, due to the pre-designed nature of the base and reduced number of mask steps for customization, while reducing unit costs over an FPGA solution. He added that the real value proposition is based on filling the gap between devices that run at volumes too high for an FPGA to make economic sense and the devices that have production volumes too low to diffuse the cost of a full-custom mask set, particularly at advanced technology nodes.

Wurman of eASIC said, “The value proposition of structured ASICs is multifold and cascading in nature, mostly driven by the dramatic reduction in NRE costs, drastically shortened TAT, the reduced need and cost of verification to the Nth decimal point, and lower tapeout costs. In other words, when the NRE is low and the TAT short, a tapeout mistake represents a much lower risk.�

Wurman added, “Reduced concern for deep-submicron design issues such as antenna effects, clock-tree balancing, power distribution, scan insertion, and so forth, result in a reduction in design time and cost. There is also a reduced need for ultra-expensive design tools to tackle deep-submicron issues-hence, a reduction in the cost of the design seat. Finally, there is a reduced risk of deep-submicron related yield issues and lower per-unit fabrication costs. And in the case of a via-only customization, there’s the elimination rather than reduction of NRE costs, with 1-week TAT and no minimum quantities.�

Vince Hopkin, vice president, Structured Digital Products AMI Semiconductor, Inc.

It’s always time to market

Chen of Faraday declared that structured ASICs offer faster time to market, a shorter development cycle for each design, much lower NRE costs, and a design flow fully compliant with cell-based approach, which means no extra place-and-route tools investment is needed and the fastest and densest array architecture is achieved. The structured ASIC also offers performance comparable to conventional standard-cell-based ASICs.

Gallagher of Synplicity noted the general value proposition comes by way of the trade-off, within 15 percent or so, between the amount of timing performance and/or area. He said the designer benefits from reduced design time, NRE, design costs, and number of design tools, as compared to cell-based ASIC. There are other values as well, depending on the vendor, he said; things such as pre-characterized IP integration, vendor-supplied design tools or flows, and migration path to cell-based.

Meanwhile, Ho of NEC gave the simple answer: “Structured ASIC architectures such as ISSP offer pre-embedded, pre-characterized features with near-cell-based ASIC performance, enable lower NREs, faster time to market, and lower design flow complexity.�

Tobias of Toshiba said these pre-defined structured array platforms try to cut the cost of deep-submicron NREs. The underlying assumption is that customers can’t afford the NRE-related mask costs of this type of customized SoC. This “structured ASIC� approach certainly addresses the NRE problem, Tobias said, but not the fundamental question: Will they provide the commercially viable customized SoC solutions that the end market needs?

Hopkin, ever feisty, took exception with Tobias. He said, “This argument totally ignores what happens if an ECO [engineering change order] is necessary, causing the mask costs to double and the cycle time to drag out 4 to 6 months.�

Tobias responded, “Structured-array based platforms save mask NRE costs and shave time to market. However, the NRE charges are dwarfed by the far bigger front-end cost of the design and development phase. This approach neither reduces development time nor minimizes design risk in a way that provides the customer with an optimized customized SoC.�

He continued, “We believe the most promising custom solution is an emerging approach that Toshiba calls ‘soft IP platforms.’ We think soft IP platforms offer the only effective solution for development of IP-rich custom SoCs today. They combat and reduce hefty up-front development costs. They allow the designer to tailor the IP content, including high-speed I/O and mixed-signal IP for the particular application. By using silicon-proven IP, they also reduce design risk and can cut overall development time from block diagram to working product by several months.�

Tobias ended by saying, “As a case in point, an SoCMosaic custom chip achieves rapid development of complex SoC designs by using commodity IP blocks, standardized bus interfaces, a scalable bus system, a register-transfer level (RTL) test bench and high-level, cycle-accurate C simulation. Pre-verified, pre-tested commodity and differentiating IP allows maximum flexibility. System-level support includes hardware and software design (with firmware and middleware) running on cycle-accurate system-level models for early development of application software.�

In response, Wurman of eASIC said the argument that the high NRE is dwarfed by the front-end design cost and hence shouldn’t be the “tail that wags the dog� seems to be contradicted by the precipitous drop in the number of ASIC design starts in recent years-a decline already in evidence prior to the downturn. Further, the high NRE is a major contributor to the increase in the cost of design, as users unable to afford a second NRE are forced to invest in massive physical verification tools and effort, to avoid the cost of extra chip spins.

Finally, Wurman said this argument ignores the impact of large TAT at 0.13 micron and below, which again forces users to heavily overspend in verification as they can’t afford the risk of losing 4 months waiting for a second spin of their chip. Consequently, it’s not that design cost dwarfs the NRE; it’s the high NRE that is largely responsible for the escalating design cost. He added that although there always will be a market for high volume, well-optimized, designs, this market seems to be limited.

Woo of Altera declared that it’s precisely this massive verification effort required today that is addressed with Altera’s HardCopy Structured ASIC, which can be prototyped with a pin-compatible, architecturally identical FPGA counterpart. The FPGA enables verification on actual silicon, with the ability to debug and verify design modification real-time at system speeds. The proven benefit of the FPGA is in the results, according to Woo. To date, every HardCopy device has taped out on schedule and worked right the first time. No re-spins will provide fastest times to market.

Woo continued, another feature providing fast time to market is that the FPGA allows designers to get a head start on the system SW development. In fact, the SW can be developed in its entirety with the FPGA, with no modifications required when it’s drop-in replaced with the HardCopy Structured ASIC

Emerging markets

Lloyd of ViASIC observed the main value proposition is a large reduction in the costs for photomasks, while still maintaining standard-cell like densities and performance. He said, “Additional value comes from simpler physical design flows and higher yields. I think the real excitement about this topic is what a structured ASIC enables, namely the creation of new electronics markets. Structured ASICs allow ideas to profitably come to market that previously did not make sense given the high start-up costs of standard-cell ASICs or the high part costs of FPGAs.�

Tralka of Xilinx opined that the value proposition for structured ASICs lies in the fact that they’re less expensive and less time consuming to develop than traditional ASICs. Interestingly though, he said, structured ASICs are being positioned against FPGAs, where neither of these value propositions apply. FPGAs have virtually no development costs and significantly lower development time than structured ASICs.

Hopkin dissented with the Xilinx statement, and said the structured ASIC value proposition also includes lower piece price, up to 90 percent lower than FPGAs.

Johnson asserted that with traditional ASIC design starts at an all time low, vendors are looking for a new value proposition. He said, “I would argue that the structured ASIC’s maybe a fine answer for the designer at the initial design/architectural decision point as an alternative to big FPGAs. However, if high volume unit price is important to the success of the project, structured ASICs will never compete with custom platform cell-based design. A piece price 90 percent lower than an FPGA can still be in excess of $200!�

Johnson added, “The right way for a design engineer to think is, ‘What can I create out of standard off-the-shelf ARM SoCs, EPLDs, and additional parts that can then be easily migrated into an ASIC, once the end product volumes justify the effort?’ In addition, mask costs for 0.18-micron standard cells designs are approaching $100K. So again, the value prop for Atmel is doing what the customer really wants and making it successful in the market. So the value prop that I’m looking forward to is making structured ASICs compatible from a design tool and methodology standpoint, and to offer a migration to cost competitive, first-time right, platform (cell-based) ASICs.�

After these preliminary questions identified the multi-faceted nature of the issue surrounding the technology, the question asked, “Why is a particular architecture a good fit for an application?�

The respondents were to address the issues of appropriate granularity, integration of existing functions and peripherals, mix of available peripherals, software support, and the negative aspects of structured ASICs including improper granularity, wrong macros, extraneous I/O cells, and the availability of appropriate synthesis tools for vairous structures.

Jay Johnson, marketing director, ASIC/ASSP Business UnitAtmel Corp.

A Preliminary Question

This question needed a precursor, however: “What is a necessary, useful, or appropriate number of programmable layers for structured ASICs?�

Marsh at Actel said, “ASIC designs vary from a few 1000’s to several million. The classic dilemma faced by ASIC gate-array providers has been, ‘How many family members?’ Too few and either the range was limited to either small or large designs, or the granularity was poor with a very limited upgrade path if a design grew larger. The more, the better may often seem the obvious choice until development costs and fab scheduling issues are considered. As a result, most gate-array providers offered about a dozen different masterslice variations per family.�

He added, “Structured array providers today face a similar problem, compounded by the need to provide a large range of device sizes for some markets, reasonably fine granularity, and various numbers of hard macro options-processors, memory, I/O, and specialized functions. It’s unlikely that the perfect combination of size /feature set can satisfy everyone. As a result, most customers will buy more silicon than they need and, as a consequence, much of the potential savings may not materialize.�

Marsh went on, “Several vendors promote the idea of a structured array as an interim step toward a standard cell solution. The idea is, a user will develop his concept in a structured array and then migrate to a ‘real’ ASIC later on as production volume grows. This now requires the user to pay for a second NRE, as well as additional design work. So if they’re not as fast as a standard cell ASIC, not as cheap in volume as a standard cell ASIC, not as flexible as an FPGA, and not as fast to market as an FPGA, but come with low NREs, who are the likely structured array users? The second- and third-tier ASIC customers who cannot afford a standard cell NRE.�

“The ASIC market is changing rapidly,� Marsh said. “Those who need less than 250,000 units are very likely to stay with FPGAs, especially with the new generation of value FPGAs now coming to market. Those who need a million-plus units will continue to use standard cell. It seems that only the few users in the middle may be candidates for structured arrays.�

“FPGAs continue to erode ASIC market share for several reasons. Design cycles continue to compress, many industries now have design cycles under 12 months or less. Many users can’t afford the time it takes to develop an ASIC, and then re-spin it to correct logic errors. In spite of better tools, the average ASIC still seems to require two or more spins to complete.�

Hopkin added his own comments on the topic, “This same argument is true of FPGAs; each family has a limited set of devices and so customers generally buy more silicon than they need. Structured ASICs are just less expensive. If designers look at the total cost of ownership considering the parameters of their particular design, they will be able to quickly determine whether an FPGA, a structured ASIC, or a cell-based ASIC approach is the most cost effective. In addition, with each successive process dimension shrink, we are seeing more and more first-tier cell-based ASIC customers who can’t afford the ASIC NRE and design cycle times. We believe the gap between FPGA and cell-based ASIC is growing, not shrinking.�

Woo answered in kind, “Determining the optimal number of programmable layers for customization requires balancing NRE prices against routing flexibility. Fewer layers will be less expensive, but will require more time and engineering effort to route. Altera makes sure we are at the ‘sweet spot’ price for NREs, while also providing a sufficient number of layers to deliver a turnkey, seamless migration from an FPGA into a HardCopy structured ASIC.�

Hopkin then said, “The number of programmable layers should be the number of layers that gives the customer the lowest NRE, while giving them the shortest timing convergence and maximizing gate utilization for a minimum die size. Having only two layers of programmability may shorten the manufacturing time over having five layers, but could increase the design routing time as the options for routing are more limited.�

Hopkin added, “If the design does not meet convergence with only two programmable layers, a larger structured ASIC base-die size may have to be used and the overall cost increases. Also, if those two programmable layers have a $44,000 per programmable metal layer NRE as the cost for a 0.13-micron process, versus a five-programmable-layer hybrid process where the reticle cost is $5,000 per programmable metal layer, the lower number of programmable layers does not always equate to the lowest customer cost. Consider $88,000 versus $25,000.�

Ze'ev Wurman, vice president, Software eASIC.

Wurman responded, “Architectures which are tuned to particular applications inherently have limited appeal and will not be major players in the marketplace. Active devices scale with technology; interconnect does not. This observation has driven the number of metal layers from 3 to 10 within the span of a decade. The natural and obvious way to tackle the combination of cheap logic and expensive interconnect, is to move to coarse-grain architectures. FPGA companies already discovered that fact more than a decade ago. In their case, their programmable interconnect was extremely expensive from day one. LUT is a wonderful logic primitive which has been proven over the years, as we have learned to effectively synthesize for it.�

“If you stick to coarse granularity,� he continued, “you can use segmented interconnect effectively and make do with a single via layer, as eASIC does. If you select a medium granularity cell like a MUX, you can survive with 2 to 3 metal layers like Lightspeed, Faraday, or NEC do. And, if you go with low-granularity cells, you end up with 4 to 5 metal layers like LSI does.�

Ho’s take on things was, “The number of programmable layers will impact several parameters-cost of NRE, turn-around time in the fab, routability and utilization, and ultimately the die size, as many others have pointed out in this forum. When NEC Electronics developed the ISSP family, we looked at many of the internal ASICs we had done, and used those real-life benchmarks to determine the layers of metal and vias to realize an optimal tradeoff amongst those parameters. In ISSP1, we believe the 2M programmable layers gave us the quick turn-around time and low NRE our customers are looking for, while still preserving within 20 percent of a full-fledged CBIC performance. As we move to ISSP 90, we may tweak the layers somewhat, since the technical and economic parameters will obviously be different.�

Gallagher said, “For applications where the density is not an issue (pad-limited designs), where routing flexibility and performance are not critical, and where time to market is critical, fewer layers would be better. For high density designs, with complex functions and performance requirements, more layers would be more desirable.�

Chen added, “Structured ASIC libraries can provide multiple derivatives for various applications. For example, a high-speed library can be used for the compute-intensive applications, while a high-density library can be used for designs with area-tight requirements.�

Tobias concluded, “The structured array concept has been around for decades, but has failed with each incarnation. The actual problem is getting from napkin to product, and that’s not what’s being solved with this hardened silicon approach. If the designer is forced to design to the array, as is the case with structured ASICs, why not just use an FPGA? If the designer must design to an architecture, making it more difficult to do the design-again, why not just use an FPGA?�

But again, Hopkin disagreed with Tobias: “The gate array is the precursor to the structured ASIC and was certainly not a failure in its day. Structured ASICs clearly fill the gap between high-NRE, high-volume, high-risk cell-based ASICs and low-NRE, high-cost, low-risk FPGAs. Granted, the full-cell-based ASIC approach gives the designer total design freedom, but at a very high cost. FPGA architectures are severely constrained, yet designers have been able to adapt their designs accordingly. Structured ASICs offer significantly more flexibility than FPGAs.�

Martice Chen, vice president, marketing and operations Faraday Technology Corp.

Fastest features

Lloyd addressed the clock implications: “Designs that require the fastest clocks possible, or the very lowest power consumption, aren't the best fit for implementation with a structured ASIC-as is true of designs that will run more than 2 million parts. These types of designs are best done in a standard-cell architecture. This 2 million parts number is higher than what some see, but I think the math and experience will show that this is the right crossover point between structured ASICs and standard-cell ASICs. Similarly, designs that will run less than 5000 parts, and don’t need high-end performance, are generally best implemented in FPGAs.�

“Structured ASICs are a good fit for most designs,� Lloyd said, “Especially those that may be re-spun, that have to get to market quickly, or that have budget constraints on NRE dollars. Just like FPGAs or gate arrays, granularity of the footprints and which hard IP is present can be confining and call for careful planning. However, we’re seeing the increased use of structured ASIC fabric as embedded blocks in an SOC. Here the structure ASIC fabric is liberating, letting customers add or change IP with a single mask change.�

Tralka said, “Having the right mix of features will be a challenge for structured ASICs, one that they are not well-equipped to manage. Xilinx is addressing this issue for our FPGAs through the ASMBL architecture approach we announced in December 2003. This architecture makes it relatively easy for us to provide the optimal mix of resources for different types of applications.�

Hopkin said, “The challenge of determining the right mix of features for structured ASICs is exactly the same challenge Xilinx faces. The ASMBL architecture appears to be a significant departure from the traditional FPGA standard product model, and a move to essentially a platform ASIC model. This model may address the needs of a small group of high-volume customers, but may abandon the needs of the smaller FPGA users.�

Wurman responded to AMI, Synplicity, and Faraday: “While it’s true that the number of customized layers in the ultimate case does affect the gate density, this issue is overemphasized. On one hand, the argument is that many designs are already IO limited. Clearly in such cases, there should be little need to optimize gate density any more than minimal customization.�

Chung Ho, director, Custom LSI SBU NEC Electronics America, Inc.

“On the other hand, if the granularity of the basic cell is large to begin with, there is little to be gained from the ability to customize metallization for features smaller than the (largish) cell size. In other words, pre-fabricated segmented routing fabric is inherently efficient with large granularity cells, as long as the synthesis to such cells is also efficient. Luckily, the industry now has over a decade of experience with effective synthesis to LUT-based fabrics. That is the reasoning behind eASIC’s large granularity LUT-based cells, and that is the reason why such technology can achieve very high gate density by customizing only the via layer.�

Johnson asked, “Isn’t the question of how many gates and layers, really the customer’s call? I have to believe it’s a tough sell if the customer’s design is only 1 million gates, but you’re trying to sell him a 3 million gate structured, pre-defined slice based on lower NREs. Again, this is really matching the customer requirement to the appropriate technology, whether gate array, platform cell-based or full custom.�

He went on, “Prove out the new IP in the design in an FPGA with Atmel’s SiliconCITY Prototyping and Emulation Platform (PEP) board, for example, and then get ready to receive first-time right silicon. The pre-defined and already validated CPU cores and IP (chip platform) can be used on the PEP (board) platform in the form of mezzanine cards that plug into the FPGA board. This eliminates the need to debug in-silicon validated IP and ultimately speeds time to market.�

How many is that?

The next question placed before the panel considered metrics: the number of metal layers, the capacity of gates per device (and how to count them), and the number of family members.

Woo said, “Determining density for a specific design is highly subjective, but right now Altera absolutely agrees that we should be using ASIC gates. Our marketing and technical collateral defines HardCopy device densities in ASIC gates, while the FPGA counterparts are stated with logic elements (4-input Look Up Tables). Our largest HardCopy device provides about a million ASIC gates of logic (not counting our embedded memory and other hard-IP functions like DSP blocks), while it’s FPGA counterpart provides about 80,000 logic elements (so we’re using about a 12:1 ASIC Gates to LE ratio).�

He added, “However, we recognize density can be subjective, so we have always made our design software very readily available so a designer can run a design through our tools and make this density determination for himself. Another important aspect is the percentage of the advertised logic capacity that can actually be utilized. Currently, we are comfortable with 90+ percent utilization in our devices, and we have achieved this high utilization by working closely with our internal software engineering teams and our software partners.�

Hopkin said, “There are two types of structured ASIC. First is a system-on-chip device with many IP blocks and one or more blocks of mask programmable fabric. The mask programmable fabric is generally pure-that is, no embedded memories. This style is essentially custom for each application enabling simplified ECOs and support of product evolution. Second is the more FPGA-like device with a mask programmable fabric block that includes embedded IP, mostly memories, timing generators, etc. This style uses the same base for multiple applications.�

He went on: “The number of gate array families however, depends on whether a structured ASIC is application specific (i.e. telecom, wireless, medical, etc.), for general usage, or specifically for FPGA conversions. For example, an application specific (platform) structured ASIC that was designed for the telecom market will have the appropriate high-speed IO structures and memory capacity to support that market, but that same platform may not support an FPGA conversion well.�

Hopkin finished: “Contrary to the thinking from the old gate-array days, gate count isn’t always a critical issue. Die size is being limited by I/O structures and amounts of memory. After placing the I/Os and the blocks of memory, logic gates are somewhat free. In the past, a ratio of memory to gates was below 0.5. Now that ratio ranges from two to four or more. Counting gates in structured ASICs can be more challenging than for cell-based designs depending on the fabric architecture. However, we believe the traditional cell-based gate counting methodology is still useful.�

Wurman said, “Clearly it’s impossible to say what is the ‘appropriate’ number of gates-it depends too much on the application. However, it is also clear that allowing programmability for only 2 to 5 percent of the gates makes little sense, as it forces the designer to pinpoint the ‘changeable logic’ with great precision up front. If it was indeed possible to predict it up front with such precision, the designer could put couple of programmable state machines or PLDs there as well, and get it done without any need for metal customization. So whatever else can be said, it’s clear that it makes little sense to have less than 20 to 30 percent customizable gates.�

“How to count the gates?� Wurman asked. “Any way desired, except such as used by Xilinx and Altera. It’s difficult to imagine a more meaningless way of counting than they already do. How many families? The fewer the better, as long as they do what they have to do well enough. FPGAs proved that one can be successful even with huge silicon penalties-30x less density, 10x lower speed and 400x more power consumption. So it seems irrational to chase marginal efficiencies in structured ASICs, where the inefficiencies are inherently much smaller, by proliferating families and slices given the huge costs associated with manufacturing and support of each slice.�

Ho said, “Counting gates have always been a tricky business. In NEC Electronics’ ISSP family, we publish Usable ASIC-equivalent gates. That’s the number we use in all our marketing collateral and technical material. The actual raw gates are a lot higher, since we assume a fairly conservative utilization factor, but the raw gate information is not very useful for our customers. In terms of what is necessary, we believe structured ASICs have to offer the type of gate densities similar to CBIC at the equivalent process node. After all, that is the integration advantage that only a mask-programmable technology can offer. In terms of the number of masters, it should be as few as possible, but still fine-grained enough so that customers are not forced to pay excessively for unnecessary silicon.�

Gallagher said, “The way to count them should always be in real ASIC gates, with achievable utilization taken into account. This way makes the decision process and migration easier to cell based for designs that reach higher volumes.�

Johnson agreed with Gallagher, “Give the customer a real migration path to standard cell designs whether starting with an FPGA or structured with metal programmable gates, but always count real ASIC gates. For example, in a Xilinx Virtex6000 that we use on our SiliconCITY PEP board, it’s about 500,000 equivalent ASIC gates.�

Whenever talking about digital designs, everyone acknowledges that on-chip memory is rapidly becoming the greatest user of silicon area in the latest designs. This design trend then leads us to the question of what is the appropriate number and size of memories in a structured ASIC?

John Gallagher, director, ASIC synthesis marketing Synplicity, inc.

Memories

Woo started, “Providing a wide enough array of products, and understanding the necessary balance between features and logic, is something Altera has been doing in designing its programmable logic products for the last 20 years. We are now extending that expertise to our HardCopy products. It’s still a matter of making sure we have the right mix of features and prices for each level.

Hopkin replied, “For a platform ASIC, this is relatively easy, as there is a certain amount of memory needed to support a particular application-such as SerDes. The higher the data rate, the more memory needed per channel. This is not so easy for either the general or conversion structured ASICs. The trend will be to pack as many memory blocks as possible into a pad-IO limited die size. This means, in some instances, that customers will be paying for memory they do not use. This is not much different from FPGAs today. These two types address the memory issue in different ways. The SoC-like structured ASICs simply embed the required memory blocks by required size and count. The FPGA-like structured ASICs have multi-mode and possibly multi-size memories that are adapted to meet the circuit requirements.�

Chen said, “Unlike FPGAs, Faraday’s Structured ASIC technology requires no memory for functional programming of the structured ASIC blocks. The memories for a particular application depend on the application requirement.�

Ho replied, “That depends on the application. We found that in networking applications, large amounts of memory are desired, while in computing and industrial applications, less on-board memory is required. In our product family, we have two roadmaps: one with a higher ratio of gate/memory, and one with a higher ratio of memory/gate.�

Wurman said, “This is the $64 million question. You can always have too little or too much memory, or you can offer two families-one memory rich and one memory poor-as some companies already do. Yet with the staggering cost of each family member, this is a very expensive gamble. And this is where LUT-based fabric also shines-SRAM is already diffused everywhere in the fabric, and it takes just a bit of ingenuity to carve it into rather efficient chunks of SRAM embedded right there with the logic where memory is needed. Chalk up another big plus for LUT-based fabric, a flexible per-user tradeoff between logic and fast memory, and hence fewer part numbers to support.�

Hopkin said, “The combination LUT/SRAM fabric is powerful and flexible at the expense of density and performance. With memory content dominating core area, LUT based memory is just not dense enough.�

Gallagher said, “Various amounts based on cell-based customer history and market application. The key thing is that there should be flexibility in memory configurations, so that the synthesis tool can actively take that into account and assign memory to the different types of memory based on performance and area tradeoffs as part of the synthesis cost function.

Richard Tobias, vice president, ASIC & Foundry Business Unit Toshiba America Electronic Components, Inc.

Tobias added, “To succeed, the pre-defined structure of a structured array must have a fairly optimized combination of gates, memory cells and other hard IP for a given design. This is unlikely to occur, given the variety of design requirements across even a small market niche. Just examine the requirements of the simplest hard IP needed for a successful SoC implementation: the SRAM.�

Tobias continued, “At Toshiba, we have been quoting designs over the last several months that use anywhere from 30 to 100 SRAM blocks of varying sizes from 2K to 120K and widths of 8- to 32-bits. The structured array approach might work if a pre-defined set of master slices could be developed with an efficient set of SRAMs that meet size, performance and physical location requirements for a given design. That’s a very big if. It requires both a very clever architectural design and that roughly 90 percent of the customer’s SoC requirement be pre-defined by the ASIC vendor up front. Varying analog spec requirements tell a similar story.�

Johnson observed, “Since memory is the most expensive silicon area commodity in ASICs, careful design considerations need to be understood. While the CPU core may only account for 4 to 5 percent of the layout, memory can be over 50 percent of the chip. Put only those critical path memories on the SoC, and then consider stacking or multi-chip packaging with an ASIC. No one talked about non-volatile memory, a core competency of Atmel, so I will.�

“In some cases, like NVM, the logic and memory process is different making it very expensive to integrate. The sweet spot for embedded flash or EEPROM at Atmel is about 2Mb. For anything more than 4Mb, we recommend dual die packaging. Remember, integration just because you can, is not always the right thing to do. Atmel doesn’t have user pre-defined memory blocks and customizes each solution for the application. I guess you could say, ‘You pay for what you get.’�

Max Lloyd, CEO, ViASIC Inc.

Should I stay or should I go?

An important question followed, “If this type of device is a hybrid between standard cell and FPGA, is it a good idea to include some programmable fabric in array?� The participants discussed the various advantages and disadvantages of doing such a technology mix.

Marsh started, “The inclusion of programmable fabric in a structured array is unlikely to be a cost effective strategy at current processes geometries. ASICs excel at area efficiency; even a structured array offers much higher packing density than possible with an FPGA-roughly 10x. If you add enough programmable fabric to a structured array, you end up with an FPGA sized device without the flexibility of an FPGA. For many applications it could be the worst of all worlds, a large die size with limited flexibility. Adding a programmable fabric compounds the already difficult decision of what features to offer in a structured array. Now a structured array vendor has to decide on memory, logic, I/Os, family members and per cent programmable logic. Conclusion? If you need the lowest cost in high volume use a std. Cell ASIC. If you need fast time to market and design flexibility use an FPGA.�

Woo said, “The inclusion of a programmable fabric in the array is good in theory. Some of the big issues, however, are the design flow and figuring out how to integrate it with the hard custom logic. It’s a good idea, with potential benefits, but it will be some time before all the implementation challenges are resolved. We recommend people use an ASIC with a small FPGA adjacent to it to make appropriate changes and updates to the design.�

Hopkin then said, “The main problem with FPGA fabric in a structured ASIC or cell-based product is the die area. Typically FPGA fabrics are 10x to 40x less dense, which means that a structured ASIC with 10-percent FPGA gates might be 90-percent FPGA area and only 10-percent structured ASIC area, clearly a very big die. FPGA fabric is always expensive; the real problem is the FPGA fabric density is an order of magnitude lower than structured ASIC fabric. Embedding FPGA fabric significantly increases die area and cost.�

Wurman added, “Embedding programmable (FPGA-like) fabric in structured array is problematic due to the huge density differential between the programmable fabric and the structured ASIC fabric. IBM and Xilinx jointly reported at ICCAD 2002 that this ratio is about 67:1, FPGA to standard cell. Hence, this ratio is about 20:1 to 30:1 for FPGA and structured ASIC. In other words, it only takes a few percent of the logic to reside in the programmable portion, to double the overall die size. Which brings us back to the argument already presented earlier; if one knows the changeable logic with such precision, there are cheaper and better ways to implement programmability rather than with a general purpose FPGA fabric. The speed differential-another factor of 5:1 or more-just makes it all the more difficult. Recall Actel’s Varicore and Adaptive Silicon.�

Chen said, “Regarding the programmable fabric in the array, the capacity of the fabric is a dominant factor affecting the area efficiency. With larger fabric, a design tends to consist of less instance count, and then the routing congestion can be reduced. However, the unused (wasted) devices do harm to the area utilization. The smaller fabric has the contrary tendency. Trade-off among fabric size, routability, and area utilization should be carefully analyzed for optimal overall performance.�

And Gallagher said, “If a real user ever stood up and showed applicability for this, then it would do both do-able and easily supported within the tool flow. The fundamental issue still seems to be that economics are so strongly in favor of having a small (now inexpensive) FPGA adjacent to the ASIC, why would you embed it in the ASIC?�

Ho said, “I assume you are talking about field-programmable fabric in a structured-ASIC? The question is about performance and cost optimization. The area/performance trade-offs in an FPGA and in an ASIC are vastly different. Putting both on the same die will force some serious compromise on either the FPGA portion or the CBIC portion. It would be difficult to hit it right on target for your customers. The tool flow consideration as mentioned by John (Synplicity) adds another layer of complexity. We feel that tradeoffs and flexibility should best addressed at the customer’s board level.�

Johnson then offered, “Atmel’s FPSLIC (AVR core + FPGA) is certainly one answer to this question. We have (small 40,000 to 80,000 gate) FPGA technology that could be used as a standard IP building block for our ASICs, if customers want it. As for any standard offering of FPGA in a structured ASIC, that’s an interesting proposition that we are looking to our customers to help us understand. Perhaps after this article is published we will have more insight.

Hammer, saw, or band saw

Last, but not least, the question of tools and methodologies comes up. The general nature of most tools seems fine for standard cells, and the tools for FPGAs handle the LUT-based functions. If the structured ASIC is a hybrid between the standard cell and LUT, then what tool or tools are most appropriate for the design? Do those tools require changes in the design tool chain? Are the emerging ESL tools better suited for design at the structured ASIC level or is the standard RTL suitable? All of this was addressed by the participants.

Woo said, “RTL tools are, in general, still adequate for current structured ASIC needs, so we’re minimizing disruption and additional investment to existing ASIC designers’ design flow to enable rapid adoption of our Structured ASIC technology. We are front-end agnostic, so HardCopy is supported with all the dominant design flows including Synopsys Design Compiler, as well as the design flows provided by Cadence, Mentor Graphics, and Synplicity. Of course, we augment all of these flows with an FPGA to simplify verification effort and eliminate physical design concerns as well as providing a vehicle to make changes in your design and confirm functionality. At the same time, we are investing in ESL tools and methodologies to be ready to provide such tools support if and when our customers require it.�

Chuck Tralka, director, product marketing, Advanced Products Group, Xilinx, Inc.

Hopkin said, “The biggest structured ASIC issue today is the place-and-route problem. Relatively speaking, cell-based design is well supported. So far, EDA vendors are trying to adapt cell-based tools to structured ASICs with only mixed results. Proprietary tools can show benefits, but are generally not supported as well as third-party cell-based tools. Timing convergence (pre and post) within place and route needs more focus from the third-party tool vendors.�

He added, “Many customers have already made a large investment in EDA tools and methodologies and would like to leverage their investment. We believe many aspects of structured ASIC design can use existing cell-based flows and methodologies, depending on how the fabric is designed. If the fabric is designed without considering the tool flow then proprietary tools must be developed. The other choice is to design the fabric from the ground up to work with existing tools.�

Wurman responded, “We need tools that will cleanly handle designs which have parts that are ‘hard’ and immutable, and portions which are still malleable-in a sense, some variant of an ECO flow. I’m not sure ESL versus RTL is the issue here. It’s more one of ESL/RTL versus ASIC (backend) tools. One of the promises of structured ASICs is to move the design community back in time, to an era in which designers could focus on the logic of the design, instead focusing on its implementation.�

Wurman added, “One of the major and overlooked tool problems which currently have no easy solution, is debugging the silicon after it comes back from the foundry. FIB is more and more expensive and less and less feasible with multi-layer metal process. An FPGA is the only solution which gives even a partial answer to the problem. But look at what eASIC offers. Having an LUT-based fabric allows easy post-silicon debug by reprogramming the logic to identify and isolate both logical and physical problems, which is the essence of the value FPGAs provide to their customers.�

Then Chen said, “A platform-based approach can offer an accelerated design cycle for large-scale and complicated designs using plenty of silicon IP. ESL helps speed up verification and implementation of large-scale SoC designs and ESL benefits designers adopting structured ASIC technology as well. However, designs with structured ASIC don’t necessarily count on such an approach. Standard RTL tools still serve well for moderate-scale designs.�

Ho said, “The design flow should match the development philosophy of structured ASICs, which means ease of use, low cost of entry, quick simulation time, with quick TAT at the design stage, and a flow optimized to take advantage of the structured ASIC gate structure.�

Wrapping up

As the conversation started to wrap up, Gallagher said, “The key thing with the tools is that they should not be the same as the tools used for either FPGAs or cell-based ASICs. Instead, they should reflect the advantages of structured/platform ASIC; namely fewer tools capable of doing more automatically based on embedded knowledge of the architectures, and ideally, jointly developed with the ASIC vendor. By developing tools and silicon together as one solution it avoids the cell-based problem where users do not have the tools necessary to access the advanced capabilities of the silicon.�

Gallagher added, “At 90 nanometers, who wouldn’t trade off 10-to-15 percent performance to have a signal integrity clean design flow that costs $30K in tools? Some wouldn’t, but considering that it represents an order of magnitude change in tool costs and half the design cycle time, with the availability of prototypes and re-spins in weeks, this clearly will enable many designers who will struggle to handle the SI and power grid design issues at 90 nanometers.�

“In terms of whether it’s an ESL market or a traditional RTL tool market, it’s definitely an RTL market today. The goal is a one-pass handoff known to be good to be quickly routed and finalized. The ESL flow may evolve to support other handoff models for structured/platform ASICs (RTL handoff), but because of the nature of the embedded methodology in the tools-in order to achieve design closure, it’s likely the handoff point will remain at the placed gates level for the next few years at least.�

Tobias said, “Toshiba developed a turn-key SoC implementation methodology for the SoCMosaic custom chip program consisting of the SoCMosaic custom chip software flow and SoCMosaic custom chip RTL flow. Once the gates netlist is sent to the physical design center, it enters a standard ASIC flow. Since there is already an existing methodology for each IP block, layout is mostly automatic, including at the design center level. This is accomplished by building a set of scripts for each set of IP that uses knowledge of what happened before. Since this IP isn’t hardened, it can be reused and modified without re-laying out each block of IP.�

Tobias concluded, “The hardware/software co-development environment allows complex software to be developed on the SoC while the chip is still in development. It uses the same programming and debugging environment throughout the process from the C model, all the way to the working end product. The first two supported co-development environments are the WhiteEagle Systems Technology Swordfish Emulation Platform, which was designed from the ground up for this program, and the proven Mentor Graphics Corp. Seamless Version 5 co-verification tool.�

Lloyd said, “Standard-RTL is by far the most popular path into our physical design tools. Traditional synthesis and traditional synthesis tools are the most used path, but I think we’ll see an increase in physical synthesis for structured ASIC that gives the designer rapid physical feedback on placement. Traditional standard-cell place-and-route tools are not a good solution for one-mask structured ASICs, but can be used for multi-layer structured ASIC architectures where routing masks can be changed. Whatever the structured architecture, new and focused tools that maximize the usage of the architecture while creating fast, simple flows are probably best for the generating the mask or masks needed for programming.�

Tralka added, “We can only comment that FPGAs, of course, are well-supported by existing tools and flows. Given that they have the widest customer base, tool support will continue to be better for FPGAs than for any ASIC and will likely be far better for than for new types of ASICs.�

Johnson had the last word: “It probably goes without saying that most of our customers use standard RTL, which ports easily into cell-based platform designs when customers bring their IP to the party. In addition, another ASIC product that Atmel has in its fold is our ULC, or Ultimate Logic Conversion, product line, which is characterized by a low-NRE, FPGA conversion business. This is where seamless FPGA and ASIC tools are most important.�

And so the conversation ended. The panel has provided their thoughts on some of the key issues on structured ASICs. Since we had no particular consensus on any of the principal issues, the challenge is left to you, the reader, to determine for yourself what specific characteristics of the structured ASIC offerings are best suited for your application. You’ll find a rich set of resources on this topic on the SemiView website (www.semiview.com). SemiView is a web-only company focused only on the issues associated with application adaptable ICs.