For many design managers, measuring design productivity may seem more difficult than improving it. While the ability to deliver increasingly complex chips all but ensures design teams are making strides toward better design productivity, quantifying this improvement can be elusive. This is due, in part, to the fact that "design productivity" means different things to different people, even within the same organization, and there are no industry-standard metrics to guide the capture and analyses of design productivity data.

Whatever the definition, demonstrating productivity gains in a given process starts with the ability and discipline to measure it. In the context of a design flow, the axiom 'you cannot improve what you cannot measure' underscores the importance of having a consistently measured set of processes to enable systematic improvement from one design to the next.

For determining what to measure, it's useful to first understand the broad set of factors that impact a designer's productivity. Recent Synopsys survey data reveals that many of the major bottlenecks experienced by designers in their chip projects are not related to the specific technical challenges in the design itself. Rather, "environmental" issues such as multi-site development teams, incoming data quality, and concurrent flow development play a significant role in the efficiency of project execution. These survey results confirm lessons learned within our own IC design services group, which tapes out dozens of chips annually for leading and mainstream chip developers.

Synopsys survey data: types and frequency of bottlenecks designers encountered on their most recent project.

A robust and integrated EDA tool platform is a prerequisite to addressing design-related productivity bottlenecks. But many environment-related issues go beyond the tools; they are greatly influenced by the design infrastructure and management practices and processes employed by the project team. To paint a more complete design productivity picture, one that comprehends both design- and environment-related factors, what gets measured should go beyond gate counts and run times. Productivity metrics constructed at a "project level" of abstraction give design managers a valuable perspective and a basis for project to project comparisons.

Let's turn our attention to identifying what to measure. While there is a myriad of data that could be recorded on any given design project, we need only focus on those metrics that are both relevant for assessing productivity at the project level and readily accessible to the team. This focus helps maintain consistency in the measurements made within a project and between projects, and lends itself to automation in collection to minimize project overhead.

After careful analysis and refinement, we've arrived at a core set of metrics that we measure for the chip design programs we execute to tapeout. These metrics include both qualitative and quantitative data points that define the design's characteristics (e.g., frequency, process geometry, IP content, etc.) and maturity (e.g., area utilization, power dissipation and negative timing slack, etc.) as well as the utilization of resources (e.g., CPU execution time, memory and tool usage, and designer effort, etc.) The complete set of metrics provides a consistent and integrated view of a design's complexity and progress towards full-chip closure in addition to the project's resource efficiency.

A well-constructed design environment, consisting of a configurable design flow as well as the infrastructure and utilities required to support the design team to a successful chip tapeout, aids designer productivity in several ways. First, the capture and reporting of many design metrics throughout the flow can be automated within the environment and without burden to the designer. In addition, a common design environment provides a consistent – and consistently measured – process that is fundamental to systematic improvement over time. This does not require that the environment remain static; in fact, a robust design environment is fully configurable for different tools, methodologies and processes, and is continuously evolving with new EDA technology and methods. Finally, the design environment can improve a designer's productivity by addressing the "environmental" bottlenecks that impact project execution, such as multi-site coordination and the qualification of incoming IP and libraries.

One standing challenge in evaluating design productivity over time or between design teams is how to compare designs which are inherently different. Virtually every project has its own unique set of characteristics and objectives that impact productivity. To avoid comparing apples to oranges, a project "normalization" methodology is needed. An approach that we have successfully implemented takes into account the key elements of design complexity such as clock frequency, instance count, memory requirements, process node, and number and quality of incoming libraries and IP blocks. In addition, application-specific intricacies such as amount of analog/mixed signal, congestion, clocking scheme and flip chip bonding must also be considered. From this information, a composite "complexity factor" can be calculated for each design project that allows project to project comparisons with reasonable correlation.

By normalizing design complexity, better correlation among varying design projects can be achieved.

To remain differentiated and cope with escalating chip complexity, continuous improvement in design productivity is an absolute necessity, and this can be measured from one project to the next with a methodology for normalizing complexity. A well-architected and maintained design environment can improve design productivity by eliminating or minimizing the non-design bottlenecks common in today's ASIC, while readily taking advantage of the productivity gains afforded by technology advanced, such as new EDA tools and computers, for example. Establishing project level metrics gives design managers a comprehensive and actionable perspective on design productivity.