Weighing the Design Requirements for 22nm Lithography
Of course, the impact of lithography on design has been considered since at least the 65nm node, as evidenced by adopting layout restrictions, such as restricted design rules, that began to appear at this node. While some layers, such as poly, were restricted to simple orientation, the complexity of interconnecting the components of a cell were pushed to the non-restricted layers and otherwise accommodated by clever reassignment of placements of transistors, for example.
The challenge of 22nm is that all of the layers involved in the logical gate formation are now facing restrictions. Also, the lower-level interconnect layers are near or below the single-exposure resolution limit. All of the patterning options being considered—double patterning, double exposure, and source-mask optimization (SMO)—require that lithography concerns be resolved earlier in the design cycle or risk complete failure at fabrication. Without proper handling at the design stage, yield will seriously affected. Each of these lithography options has benefits, restrictions, and costs that must be weighed against the design requirements.
Double patterning is the realization of the original design shapes by two or more independent patterning (imaging) steps. There are multiple methods for double patterning but they share the design constraint that all groupings of design shapes must be evenly divisible into two groups. The groupings typically can be associated with a space between shapes so the killer design is the one where an odd number of critical spaces all must be honored, since an odd integer cannot be decomposed into a pair of integers. This is called a cycle conflict. Cycle conflict can be local to functional gate cells, in between these gate cells, or also in the cell-to-cell routing. Designs with no cycle conflicts can achieve the highest density. The higher density comes at the expense of increased process cost; roughly twice the cost of single exposure, although research into lower cost process options is ongoing. One processing option for double patterning, called spacer, would impose the most restrictive design rules on the layers using it, but it avoids the higher costs and some of the manufacturing variability of other double patterning choices.
Double exposure reduces the processing cost considerably from double patterning by combining a series of processing steps into one. This lowered process cost, however, restricts the resolution capability and thus the achievable density of the design. In order to keep density as high as possible with double exposure, a fairly restrictive illumination is chosen—typically two dipole illuminators—and this causes strong interactions between the illuminations that tend to limit the types of two-dimensional structures that can be supported. The impact to design manifests in the restrictions of small jogs or stubs, which can seem to increase density but possibly become irresolvable. In other words, the impacts tend to be localized but are not easily captured in classic design rules due to interactions with neighbors.
Source-mask optimization (SMO) holds the promise of the least design restrictions for the densest portions of the design. SMO can’t achieve the density of double patterning, but by utilizing the flexibility of both the source illumination and the mask shapes it is able to adapt to the design more than the other methods. One of the main strengths of SMO is that source illumination pattern adaptation occurs per design, compared to the classic approach of optimizing only the mask per design while keeping the source static. Of course, due to this adaptability, SMO can also be combined with either double patterning or double exposure to limit the design restrictions that are required by these techniques, except for cycle conflict. At Mentor Graphics, we have been working with IBM to develop SMO for the 22nm node. Because we’ve been able to develop software and perform silicon validation simultaneously, we’ve made great strides in addressing the critical elements required for achieving full-chip SMO.
The foundries are actively exploring all of these process options in order to provide the design rules needed at the start of IC/SoC design work. For each of the layers requiring these advanced techniques, designers and their vendors must develop a robust solution for each of the lithography options in order to select the one they will offer to their customers and use to compete with one another. Software companies like Mentor Graphics are developing, or have available, tools (such as cycle conflict detection) for evaluating existing designs that need to be migrated, as well as design tools to enable successful design creation with these process options.
For designers, the first step is to consider the requirements of the target design. For example, if a design is targeting maximum density, double patterning is the only viable alternative. That, in turn, may force re-design of existing components, which greatly increases the cost and time to market of a design. To mitigate the double pattering costs, you would need to carefully evaluate third-party IP, limit double patterning to the layers requiring maximum density, and ramp up on any new tools and methodologies needed for pattern decomposition. On the positive side, double patterning may open new avenues to support specific concerns such as lowering the power budgets, using high-throughput tools and scanners, and achieving acceptable critical dimension (CD) uniformity. All these considerations start at the earliest stages of the design and need to be quantified in terms of time, cost, and feasibility.
These restrictions can partially be captured in classic design rules, and the portions which cannot are recognized with newer lithography simulations embedded in litho-friendly design (LFD) tools, such as Mentor’s Calibre LFD.
The economics of designing for advanced lithography comes with complex tradeoffs. All the options are becoming more computationally intense, and so demand the establishment of new methodologies, the use of new tools, and improved computational throughput. Designers need to learn about all the options, and how to best combine them for specific design, cost, and time-to-market goals. Weighing these options will require closer cooperation between the design house, the software and equipment vendors, and the fabs.