Synopsys today took the covers off its long-awaited solution to algorithmically intensive designs, rolling out a high-level synthesis solution that makes it easier to move designs from Matlab into RTL.
 
Both Mentor Graphics and Cadence have tools in this area, and Synopsys had been rumored to be working on this type of solution for some time (see "Verification as a Deterrent").  Synopsys’ entry into the market is further recognition of just how complex designs have become and where the pain points are. It also provides a glimpse into how Synopsys is leveraging its $227 million acquisition of FPGA tools vendor Synplicity in March 2008.

Algorithms have been used extensively as a way of reducing power and boosting performance in a variety of chips, but most of the algorithms are written in floating point with little concern about implementation. They need to be converted to fixed point to build chips, and making the leap from one to the next is like crossing a fast-moving river with no bridge. It can be done, but the results aren’t always predictable.

Chris Eddington, director of marketing for Synopsys’ high-level synthesis and system-level products, said Synopsys has been seeing this problem in both the FPGA and ASIC worlds, particularly in designs involving near-field communications or those with multiple antennae and specialized baseband.

"What we’re seeing is a crisis in verification," Eddington said. "You integrate all the subsystems and then find bugs after tapeout. There’s too much complexity. You can’t get the verification done early enough. That’s particularly true with algorithmic validation."

Synopsys’ new Synphony product adds automated flow from M to RTL, synthesis of RTL architectures for ASICs and FPGAs, rapid prototyping for early algorithm validation and unified verification across a number of flows such as prototyping and ASIC implementation.